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Digital Controller for Isolated Power Supply Applications ADP1043A
FEATURES
Integrates all typical controller functions Digital control loop Remote and local voltage sense Primary and secondary side current sense PWM control Synchronous rectifier control Current sharing Integrated programmable loop filter I2C interface Extensive fault detection and protection Extensive programming Fast calibration EEPROM Standalone or microcontroller control
GENERAL DESCRIPTION
The ADP1043A is a secondary side power supply controller IC designed to provide all the functions that are typically needed in an ac-to-dc or isolated dc-to-dc control application. The ADP1043A is optimized for minimal component count, maximum flexibility, and minimum design time. Features include remote voltage sense, local voltage sense, primary and secondary side current sense, pulse-width modulation (PWM) generation, and hot-swap sense and control. The control loop is digital with an integrated programmable digital filter. Protection features include current limiting, ac sense, undervoltage lockout (UVLO), and overvoltage protection (OVP). The built-in EEPROM provides extensive programming of the integrated loop filter, PWM signal timing, inrush current, and soft start timing and sequencing. Reliability is improved through a built-in checksum and redundancy of critical circuits. A comprehensive GUI is provided for easy design of loop filter characteristics and programming of the safety features. The industry-standard I2C bus provides access to the many monitoring and system test functions. The ADP1043A is available in a 32-lead LFCSP and operates from a single 3.3 V supply.
APPLICATIONS
AC-to-DC power supplies Isolated dc-to-dc power supplies Redundant power supplies Parallel power supplies Server, storage, network, and communications infrastructure
TYPICAL APPLICATION CIRCUIT
PFC
AC INPUT
LOAD
DRIVER DRIVER SR1 SR2 CS1 OUTA OUTB OUTC OUTD OUTAUX RES ADD RTD VCORE FLAGIN PSON PGOOD2 PGOOD1 SDA SCL ACSNS PGND CS2- CS2+ VS1 GATE VS2
VS3+ VS3- SHAREo SHAREi
DRIVER
ADuM1410
VDD DGND AGND
VDD
08501-001
MICROCONTROLLER
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
ADP1043A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Typical Application Circuit ............................................................. 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications..................................................................................... 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 Soldering ........................................................................................ 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 12 Current Sense .............................................................................. 12 Voltage Sense and Control Loop .............................................. 13 ADCs ............................................................................................ 13 Digital Filter ................................................................................ 14 PWM and Sync Rect Outputs (OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2) ................................................... 14 Synchronous Rectification ........................................................ 15 Adaptive Dead Time Control.................................................... 15 Light Load Mode ........................................................................ 15 Modulation Limit ....................................................................... 15 OrFET Control (GATE) ............................................................ 15 VDD ............................................................................................. 18 VDD/VCORE OVLO ................................................................ 18 Power Good................................................................................. 18 Soft Start ...................................................................................... 19 Current Sharing (Share) ............................................................ 20 Power Supply System and Fault Monitoring ............................... 22 Flags .............................................................................................. 22 Monitoring Functions ................................................................ 22 Voltage Readings ........................................................................ 22 Current Readings........................................................................ 22 Power Readings........................................................................... 23 Power Monitoring Accuracy ..................................................... 23 First Flag Fault ID and Value Registers ................................... 23 External Flag Input (FLAGIN Pin) .......................................... 23 Temperature Readings (RTD Pin)............................................ 23 Overtemperature Protection (OTP) ........................................ 23 Overcurrent Protection (OCP) ................................................ 24 Constant Current Mode ............................................................ 25 Overvoltage Protection (OVP) ................................................. 25 Undervoltage Protection (UVP) .............................................. 25 AC Sense (ACSNS)..................................................................... 26 Volt-Second Balance .................................................................. 26 Load Line ..................................................................................... 26 Power Supply Calibration and Trim ............................................ 27 CS1 Trim...................................................................................... 27 CS2 Trim...................................................................................... 27 Voltage Calibration and Trim ................................................... 27 Output Voltage Setting (VS3+, VS3- Trim) ........................... 28 VS1 Trim...................................................................................... 28 VS2 Trim...................................................................................... 28 RTD/OTP Trim .......................................................................... 28 Layout Guidelines....................................................................... 28 Communication.............................................................................. 29 I2C Interface ................................................................................ 29 EEPROM ..................................................................................... 31 Software GUI .............................................................................. 32 Register Listing ............................................................................... 33 Detailed Register Descriptions ..................................................... 35 Fault Registers ............................................................................. 35 Value Registers ............................................................................ 38 Current Sense and Current Limit Registers............................ 41 Voltage Sense Registers .............................................................. 46 ID Registers ................................................................................. 49 PWM and Synchronous Rectifier Timing Registers ............. 50 Digital Filter Programming Registers ...................................... 58 Adaptive Dead Time Registers ................................................. 60 EEPROM Registers .................................................................... 64 Resonant Mode Operation ............................................................ 65 Resonant Mode Enable .............................................................. 65 PWM Timing in Resonant Mode............................................. 65 Synchronous Rectification in Resonant Mode ....................... 65 Adjusting the Timing of the PWM Outputs ........................... 66 Frequency Limit Setting ............................................................ 66 Feedback Control in Resonant Mode ...................................... 66 Soft Start in Resonant Mode ..................................................... 66
Rev. 0 | Page 2 of 72
ADP1043A
Light Load Operation (Burst Mode) ........................................66 OUTAUX in Resonant Mode ....................................................66 Protections in Resonant Mode ..................................................66 Resonant Mode Register Descriptions ..................................... 67 Outline Dimensions ........................................................................ 71 Ordering Guide ........................................................................... 71
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 3 of 72
ADP1043A
The ADP1043A is a secondary side controller for switch mode power supplies (SMPS). It is designed for use in isolated redundant applications. The ADP1043A integrates the typical functions that are needed to control a power supply. These include * * * * * * * * Output voltage sense and feedback Digital loop filter compensation PWM generation Current sharing Current, voltage, and temperature sense OrFET control Housekeeping and I2C interface Calibration and trimming A current share bus interface provides for parallel power supplies. The part also has hot-swap OrFET sense and control for N + 1 redundant power supplies. Conventional power supply housekeeping features, such as remote and local voltage sense and primary and secondary side current sense, are included. An extensive set of protections is offered, including overvoltage protection (OVP), overcurrent protection (OCP), overtemperature protection (OTP), undervoltage protection (UVP), ground continuity monitoring, and ac sense. All these features are programmable through the I2C bus interface. This bus interface is also used to calibrate the power supply. Other information, such as input current, output current, and fault flags, is also available through the I2C bus interface. The internal EEPROM can store all programmed values and allows standalone control without a microcontroller. A free, downloadable GUI is available that provides all the necessary software to program the ADP1043A. For more information about the GUI, contact Analog Devices, Inc., for the latest software and a user guide. The ADP1043A operates from a single 3.3 V supply and is specified from -40C to +85C.
The main function of controlling the output voltage is performed using the feedback ADCs, the digital loop filter, and the PWM block. The feedback ADCs use a multipath approach (patent pending). The ADP1043A combines a high speed, low resolution (fast and coarse) ADC and a low speed, high resolution (slow and accurate) ADC. Loop compensation is implemented using the digital filter. This PID (proportional, integral, derivative) filter is implemented in the digital domain to allow easy programming of filter characteristics, which is of great value in customizing and debugging designs. The PWM block generates up to seven programmable PWM outputs for control of FET drivers and synchronous rectification FET drivers. This programmability allows many traditional and unique switching topologies to be realized.
FUNCTIONAL BLOCK DIAGRAM
ACSNS PGND GATE CS2+ CS2- VS1 VS2 ADC ADC VS3+ VS3- SHAREo PWM ENGINE DIGITAL CORE 8kB EEPROM I2C INTERFACE ADC LDO VCORE RES AGND FLAGIN DGND OSC PSON SCL
08501-002
VREF
CS1 SR1 SR2 OUTA OUTB OUTC OUTD OUTAUX VDD
ADC
ADC
ADC
PWM SHAREi PGOOD1
PGOOD2
UVLO
SDA ADD RTD
Figure 2.
Rev. 0 | Page 4 of 72
ADP1043A SPECIFICATIONS
VDD = 3.3 V, TA = -40C to +85C, unless otherwise noted. FSR = full-scale range. Table 1.
Parameter SUPPLY VDD IDD Symbol VDD IDD Test Conditions/Comments Min 3.1 Normal operation (PSON is high) Power supply off (PSON is low) During EEPROM programming (40 ms) VDD rising VDD falling 3.05 2.75 3.7 TA = 25C RES = 49.9 k 2.3 190 Typ 3.3 20 15 IDD + 8 Max 3.6 Unit V mA mA mA V V mV V V MHz
POWER-ON RESET Power-On Reset UVLO UVLO Hysteresis OVLO VCORE PIN Output Voltage OSCILLATOR AND PLL PLL Frequency OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2 PINS Output Low Voltage Output High Voltage Rise Time Fall Time AC SENSE Input Voltage Threshold Propagation Delay VS1, VS2, VS3 LOW SPEED ADC Input Voltage Range Sampling Frequency Voltage Sense Measurement Accuracy
2.85 35 3.9 2.5 200
2.95 4.1 2.7 210
VOL VOH
Source current = 10 mA Source current = 10 mA CLOAD = 50 pF CLOAD = 50 pF PWM and resonant mode From ACSNS threshold to SR start; resonant mode only
0.4 VDD - 0.4 3.5 1.5 0.3 0.45 160 0.65
V V ns ns V ns
VIN fSAMP
Differential voltage from VS1, VS2 to PGND, and from VS3+ to VS3- From 0% to 100% of input voltage range
0
1 100
1.55
V Hz % FSR mV % FSR mV % FSR mV Bits mV s % s %
-10 -155 -2.5 -38.75 -1.5 -23.25 12 -200
+10 +155 +2.5 +38.75 +1.5 +23.25
From 10% to 90% of input voltage range From 900 mV to 1.1 V Voltage Sense Measurement Resolution Voltage Differential from VS3- to PGND VS1 OVP Comparator Speed VS1 OVP Threshold Accuracy VS2 and VS3 OVP Comparator Speed VS2 and VS3 OVP Threshold Accuracy VS1 HIGH SPEED ADC Sampling Frequency Resolution Dynamic Range
+200 300 2.5 300 2.5
Register 0x2C[2] = 0 Relative to nominal voltage (1 V) on VS1 Register 0x2C[2] = 0 Relative to nominal voltage (1 V) on VS2 and VS3 fSAMP
400 6 18
Rev. 0 | Page 5 of 72
kHz Bits mV
ADP1043A
Parameter CURRENT SENSE 1 (CS1 PIN) Input Voltage Range Sampling Frequency Current Sense Measurement Accuracy Symbol VIN fSAMP From 10% to 90% of input voltage range Test Conditions/Comments Min 0 -3.0 -41.4 -10 -138 12 1.1 From 10% to 90% of input voltage range -3.0 -41.4 10 4.0 1.2 80 1.3 100 +3.0 +41.4 Typ 1 100 Max 1.38 +3.0 +41.4 +10 +138 Unit V Hz % FSR mV % FSR mV Bits V ns % FSR mV ms A
From 0% to 100% of input voltage range Current Sense Measurement Resolution CS1 Fast OCP Threshold CS1 Fast OCP Speed CS1 Accurate OCP DC Accuracy CS1 Accurate OCP Speed Leakage Current CURRENT SENSE 2 (CS2+, CS2- PINS) Input Voltage Range ADC Input Voltage Range Sampling Frequency Current Sense Measurement Accuracy
VIN fSAMP
Differential voltage from CS2+ to CS2- LSB = 61.04 V From 0 mV to 200 mV From 200 mV to 225 mV
-100 0 100 -4 -15 -7.5 12
+225 225 +4 +15 +7.5
mV mV Hz mV mV % FSR Bits mV mV % FSR ms A A V
Current Sense Measurement Resolution CS2 Accurate OCP Accuracy
From 0 mV to 200 mV From 200 mV to 225 mV
-4 -15 -7.5 10 100 100 1
+4 +15 +7.5
CS2 Accurate OCP Speed Current Sink (High Side) Current Source (Low Side) Common-Mode Voltage at the CS2+ and CS2- Pins GATE PIN (OPEN DRAIN) Output Low Voltage OrFET PROTECTION (CS2+, CS2-) Accurate OrFET Threshold Accuracy Accurate OrFET Speed Fast OrFET Accuracy
To achieve CS2 measurement accuracy
0.8
1.3
VOL Low-side current sensing only -1.2 0 10 -25 -50 -75 -100 110 1 10.8
0.4 +1
V mV ms mV mV mV mV ns V A % FSR mV % FSR mV
Fast OrFET Speed RTD PIN Input Voltage Range Current Source RTD ADC Measurement Accuracy
-25 mV setting -50 mV setting -75 mV setting -100 mV setting Debounce = 40 ns VIN RTD resistor = 100 k From 2% to 20% of input voltage range From 32 mV to 320 mV From 0% to 100% of input voltage range From 0 V to 1.55 V
Rev. 0 | Page 6 of 72
-40 -70 -100 -125
-10 -30 -50 -75 150 1.55 12 +1 +15.5 +10 +155
0 9.5 -1 -15.5 -10 -155
ADP1043A
Parameter OTP Threshold Accuracy Symbol Test Conditions/Comments When RTD = 10 k When RTD = 100 k OTP Speed OTP Threshold Hysteresis PGOOD1, PGOOD2, SHAREo PINS (OPEN DRAIN) Output Low Voltage PSON, FLAGIN, SHAREi PINS (DIGITAL INPUTS) Input Low Voltage Input High Voltage SDA/SCL PINS Input Low Voltage Input High Voltage Output Low Voltage Leakage Current SERIAL BUS TIMING Clock Frequency Glitch Immunity Bus-Free Time Start Setup Time Start Hold Time SCL Low Time SCL High Time SCL, SDA Rise Time SCL, SDA Fall Time Data Setup Time Data Hold Time EEPROM RELIABILITY Endurance 1 Data Retention 2
1 2
Min -0.5 -7.75 -5 -77.5
Typ
Max +0.5 +7.75 +5 +77.5
When RTD = 10 k
10 16
Unit % FSR mV % FSR mV ms mV
VOL
0.4
V
VIL VIH VDD = 3.3 V VIL VIH VOL
0.4 VDD - 0.8 0.4 VDD - 0.8 -5 100 0.4 +5 400 50
V V V V V A kHz ns s s s s s ns ns ns ns Cycles Years
tSW tBUF tSU;STA tHD;STA tLOW tHIGH tR tF tSU;DAT tHD;DAT
4.7 4.7 4 4.7 4 1000 300 250 300 10,000 20
TJ = 85C
Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at -40C, +25C, +85C, and +125C. Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
Rev. 0 | Page 7 of 72
ADP1043A ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage (Continuous) VDD Digital Pins VS3- to PGND, AGND, DGND RTD, VS1 to AGND VS2, VS3+, ADD to AGND Operating Temperature Range Storage Temperature Range Junction Temperature Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) RoHS-Compliant Assemblies (20 sec to 40 sec) ESD Charged Device Model ESD Human Body Model Rating 4.2 V -0.3 V to VDD + 0.3 V -0.3 V to +0.3 V 2.5 V -0.3 V to VDD + 0.3 V -40C to +85C -65C to +150C 150C 240C 260C 1.5 kV 3.5 kV
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type 32-Lead LFCSP JA 44.4 JC 6.4 Unit C/W
SOLDERING
It is important to follow the correct guidelines when laying out the PCB footprint for the ADP1043A and when soldering the part onto the PCB. The AN-772 Application Note discusses this topic in detail (see www.analog.com).
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 8 of 72
ADP1043A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
24 23 22 21 20 19 18 17
VS3+ VS3- RES ADD RTD VDD VCORE DGND
VS2 AGND VS1 CS2- CS2+ ACSNS CS1 PGND
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
TOP VIEW (Not to Scale)
SHAREi SHAREo PGOOD1 PGOOD2 FLAGIN PSON SDA SCL
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 Mnemonic VS2 Description Power Supply Output Sense Input. This signal is referred to PGND. Input to a low frequency - ADC. Nominal voltage at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. Analog Ground. This pin is the ground for the analog circuitry of the ADP1043A. Star connect to DGND. Local Voltage Sense Input. This signal is referred to PGND. Input to a high frequency - ADC. Nominal voltage at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. Inverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. When using high-side current sensing in a 12 V application, place a 110 k resistor between the sense resistor and this pin. When using low-side current sensing, place a 10 k resistor between the sense resistor and this pin. When using high-side current sensing, use the formula R = (VCOMMONMODE - 1)/100 A. A 0.1% resistor must be used to connect this circuit. Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. When using high-side current sensing in a 12 V application, place a 110 k resistor between the sense resistor and this pin. When using low-side current sensing, place a 10 k resistor between the sense resistor and this pin. When using high-side current sensing, use the formula R = (VCOMMONMODE - 1)/100 A. A 0.1% resistor must be used to connect this circuit. AC Sense Input. This input is connected upstream of the main inductor through a resistor divider network. The nominal voltage for this circuit is 0.45 V. This signal is referred to PGND. Primary Side Current Sense Input. This pin is the current transformer input to measure and control the primary side current. This signal is referred to PGND. The resistors on this input must have a tolerance specification of 0.5% or better to allow for trimming. Power Ground. This pin is the ground connection for the main power rail of the power supply. Star connect to AGND. Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled when not in use. This signal is referred to AGND. Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. Auxiliary PWM Output. This pin can be disabled when not in use. This signal is referred to AGND. OrFET Gate Drive Output (Open Drain). This signal is referred to AGND. I2C Serial Clock Input. This signal is referred to AGND. I2C Serial Data Input and Output (Open Drain). This signal is referred to AGND.
Rev. 0 | Page 9 of 72
2 3
AGND VS1
4
CS2-
5
CS2+
6 7
ACSNS CS1
8 9 10 11 12 13 14 15 16 17 18
PGND SR1 SR2 OUTA OUTB OUTC OUTD OUTAUX GATE SCL SDA
08501-003
NOTES 1. THE ADP1043A HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDE OF THE PACKAGE. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE PCB GROUND PLANE.
SR1 SR2 OUTA OUTB OUTC OUTD OUTAUX GATE
9 10 11 12 13 14 15 16
ADP1043A
Pin No. 19 20 21 22 Mnemonic PSON FLAGIN PGOOD2 PGOOD1 Description Power Supply On Input. This signal is referred to DGND. This is the hardware PSON control signal. It is recommended that a 1 nF capacitor be included from the PSON pin to DGND for noise debounce and decoupling. Flag Input. An external signal can be input at this pin to generate a flag condition. Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD2 flag. This pin is set if any flag is set. Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD1 flag. This pin is set if any of the following are out of range: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, or load OVP. Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a 2.2 k resistor. When configured as a digital share bus, this pin is a digital output. This signal is referred to AGND. Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referred to AGND. Digital Ground. This pin is the ground for the digital circuitry of the ADP1043A. Star connect to AGND. Output of 2.5 V Regulator. Connect a 100 nF capacitor from this pin to DGND. Positive Supply Input. Range is from 3.1 V to 3.6 V. This signal is referred to AGND. Thermistor Input. A 100 k thermistor is placed from this pin to AGND. This signal is referred to AGND. Address Select Input. Connect a resistor from ADD to AGND. This signal is referred to AGND. Resistor Input. This pin sets up the internal voltage reference for the ADP1043A. Connect a 49.9 k resistor (0.1%) from RES to AGND. This signal is referred to AGND. Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. Noninverting Remote Voltage Sense Input. This signal is referred to VS3-. Use 0.1% resistors as the resistor divider to connect this circuit. The resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. The ADP1043A has an exposed thermal pad on the underside of the package. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the PCB ground plane.
23 24 25 26 27 28 29 30 31 32
SHAREo SHAREi DGND VCORE VDD RTD ADD RES VS3- VS3+
Exposed Pad
EP
Rev. 0 | Page 10 of 72
ADP1043A TYPICAL PERFORMANCE CHARACTERISTICS
4 3
CS1 ADC ACCURACY (%FSR)
4 3 2 1 0 -1 -2 -3 MEAN MIN 0 MAX 20 MIN SPEC 40 MAX SPEC
08501-004
VS1 ADC ACCURACY (%FSR)
2 1 0 -1 -2 -3 -4 -40
MEAN MIN_N10%
MIN
MAX MAX_P10%
MIN SPEC
MAX SPEC
-20
60
80
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 4. VS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Figure 7. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
4 3
6
4
VS2 ADC ACCURACY (%FSR) 2 1 0 -1 -2 -3 MEAN -4 -40 -20 MIN 0 MAX 20 MIN SPEC 40 MAX SPEC
08501-005
CS2 ADC ACCURACY (%FSR)
2
0
-2
-4 MEAN MIN_P10% -6 -40 -20 0 MIN MAX MAX_P10% 20 MIN SPEC MAX_N10% 40 60 80
08501-008 08501-009
MAX SPEC
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. VS2 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Figure 8. CS2 ADC Accuracy vs. Temperature (from 0 mV to 200 mV)
4 3 2 1 0 -1 -2 -3 -4 -40 MEAN MIN_P10% -20 0 MIN MAX MAX_N10%
08501-006
1.35
CS1 FAST OCP THRESHOLD (V)
1.30
VS3 ADC ACCURACY (%FSR)
1.25
1.20
1.15
1.10 MEAN 1.05 -40 -20 MIN 0 MAX 20 MIN SPEC 40 60 MAX SPEC 80
MIN SPEC
MAX SPEC
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
Figure 6. VS3 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Figure 9. CS1 Fast OCP Threshold vs. Temperature
Rev. 0 | Page 11 of 72
08501-007
-4 -40
ADP1043A THEORY OF OPERATION
CURRENT SENSE
The ADP1043A has two individual current sense inputs: CS1 and CS2. These inputs sense, protect, and control the output current and the share bus information. They can be calibrated to remove any errors due to external components.
CS2 Operation (CS2+, CS2-)
CS2 is used for the monitoring and protection of the secondary side current. The full-scale range of the CS2 ADC is 225 mV. The nominal full load voltage drop can be configured for 37.5 mV, 75 mV, or 150 mV. The differential inputs are fed into an ADC through a pair of external resistors. When using low-side current sensing, a 10 k resistor is required. When using high-side current sensing, a 110 k resistor is required (for a 12 V application). Low-side current sensing is recommended because it provides improved performance compared with high-side current sensing. High-side current sensing is not supported for applications where the output voltage is above 20 V common mode. (There is not enough offset trim range above 20 V common mode.) Typical configurations are shown in Figure 11 and Figure 12. Various thresholds and limits can be set for CS2, such as OCP. These thresholds and limits are described in the Current Sense and Current Limit Registers section. When not in use, both CS2 inputs should be connected through 10 k resistors to PGND.
CS1 Operation (CS1)
CS1 is typically used for the monitoring and protection of the primary side current. This is commonly known as the current transformer (CT) method of current sensing. The input signal at the CS1 pin is fed into an ADC for current monitoring. The range of the ADC is 0 V to 1.38 V. The input signal is also fed into a comparator for fast OCP protection. The typical configuration for the current sense is shown in Figure 10.
VIN OUTA OUTC
OUTB
OUTD
I = 10A 1k 10
1V I = 100mA
CS1
I
12V
ADC
12 BITS
VREF 1:100
FAST OCP
08501-010
110k CS2+
110k CS2-
Figure 10. Current Sense 1 (CS1) Operation
1V
ADC
12 BITS
The comparator effectively measures peak current, and the ADC effectively measures the average current information. This information is available through the I2C interface. Various thresholds and limits can be set for CS1, such as OCP. These thresholds and limits are described in the Current Sense and Current Limit Registers section.
Figure 11. High-Side Resistive Current Sense
I 10k CS2- 10k CS2+
1V 100A 100A
ADC
12 BITS
Figure 12. Low-Side Resistive Current Sense (Recommended)
Rev. 0 | Page 12 of 72
08501-012
08501-011
100A
100A
ADP1043A
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the ADP1043A are used for the monitoring, control, and protection of the power supply output. The voltage information is available through the I2C interface. All voltage sense points can be calibrated digitally to remove any errors due to external components. This calibration can be performed in the production environment, and the settings can be stored in the EEPROM of the ADP1043A (see the Power Supply Calibration and Trim section for more information). The update rate of the ADC from a control loop standpoint is set to the switching frequency. Therefore, if the switching frequency is set to 100 kHz, the ADC outputs a signal every 100 kHz to the control loop. Because the - modulators of the ADC sample at 1.6 MHz, the output of the ADC is the average of the 16 readings taken during the 1.6 MHz time frame. For voltage monitoring, the VS1, VS2, and VS3 voltage value registers are updated every 10 ms. The ADP1043A stores every ADC sample for 10 ms and then outputs the average value at the end of the 10 ms period. Therefore, if these registers are read at least every 10 ms, a true average value is read. The same applies to the CS1 and CS2 current readings. For the control loop, the high speed signal always comes from the VS1 high speed ADC. The low speed signal normally comes from the VS3 low speed ADC. However, during soft start or in response to a load OVP or other fault condition, the ADP1043A can switch its low speed regulating point from VS3 to VS1.
12V 12V 12V
VS1 Operation (VS1)
VS1 is used for the monitoring and protection of the power supply voltage at the output of the LC stage, upstream of the OrFET. This is also the high frequency feedback loop for the power supply. The VS1 sense point on the power rail needs an external resistor divider to bring the nominal common-mode signal to 1 V at the VS1 pin (see Figure 13). The resistor divider is necessary because the ADP1043A VS1 ADC input range is 0 V to 1.55 V. This divided-down signal is internally fed into a high speed and a low speed - ADC. The output of the VS1 ADCs goes to the digital filter. The high speed ADC has a 2 MHz bandwidth and is run from a 25 MHz clock. It has a range of 18 mV. When the sampling rate is 200 kHz, there is 0.6 mV (two LSBs) of quantization noise. Increasing the sampling rate to 400 kHz increases the quantization noise to 1.2 mV. In the event of a load overvoltage condition, the power supply is regulated from the VS1 sense point, rather than from the VS3 sense point.
VS2 Operation (VS2)
VS2 is typically used for the monitoring and protection of the output of the power supply, downstream of the OrFET. It is used with VS1 to control the OrFET gate drive turn-on. The VS2 sense point on the power rail needs an external resistor divider to bring the nominal common-mode signal to 1 V at the VS2 pin (see Figure 13). The resistor divider is necessary because the ADP1043A VS2 ADC input range is 0 V to 1.55 V. This divided-down signal is internally fed into an ADC. The output of the VS2 ADC goes to the VS2 voltage value register (Register 0x16).
LOAD
11k 1V 1k 1V
11k 1k
VS3 Operation (VS3+, VS3-)
VS3 is used for the monitoring and protection of the remote load voltage. It is a fully differential input. This is the main feedback sense point for the power supply control loop. The VS3 sense point on the power rail needs an external resistor divider to bring the nominal common-mode signal to 1 V at the VS3 pins (see Figure 13). The resistor divider is necessary because the ADP1043A VS3 ADC input range is 0 V to 1.55 V. This divided-down signal is internally fed into an ADC. The output of the VS3 ADC goes to the digital filter.
PGND
VS1
VS2 11k VS3+ VS3- 1V 1k
VS1 HIGH ADC SPEED 6 BITS HIGH FREQUENCY FEEDBACK LOOP
VS1 LOW ADC SPEED 12 BITS
VS2 ADC 12 BITS
VS3 ADC 12 BITS
ADCs
LOW FREQUENCY FEEDBACK LOOP
08501-013
DIGITAL FILTER
Figure 13. Voltage Sense Configuration
The ADP1043A includes several ADCs. The high speed ADC is described in the VS1 Operation (VS1) section. The other ADCs are low speed, high resolution. They have a 1 kHz bandwidth and 12-bit resolution. Each ADC has its own voltage reference for added protection from potential failure. The digital output of each ADC is readable through the appropriate value register.
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ADP1043A
DIGITAL FILTER
The loop response of the power supply can be changed using the internal programmable digital filter. A Type 3 filter architecture has been implemented. To tailor the loop response to the specific application, the low frequency gain, zero location, pole location, and high frequency gain can all be set individually (see the Digital Filter Programming Registers section). It is recommended that the Analog Devices software GUI be used to program the filter. The software GUI displays the filter response in Bode plot format and can be used to calculate all stability criteria for the power supply. From the sensed voltage to the duty cycle, the transfer function of the filter in z-domain is as follows:
The Analog Devices software GUI allows the user to program the light load mode filter in the same manner as the normal mode filter. It is recommended that the GUI be used for this purpose. In addition, during the soft start process, a different set of digital filters is used. The soft start filter value for a, b, and c in Equation 1 is 0, and the d value is programmed through the soft start filter gain setting (Register 0x5F[1:0]).
PWM AND SYNC RECT OUTPUTS (OUTA, OUTB, OUTC, OUTD, OUTAUX, SR1, SR2)
The PWM and SR outputs are used for control of the primary side drivers and the synchronous rectifier drivers. These outputs can be used for several control topologies, including full-bridge, phase-shifted ZVS, and interleaved two switch forward converter configurations. Delays between rising and falling edges can be individually programmed. Special care must be taken to avoid shoot-through and cross-conduction. It is recommended that the Analog Devices software GUI be used to program these outputs. Figure 14 shows an example configuration to drive a full-bridge, phase shift topology with synchronous rectification.
VIN OUTA OUTC
d z H(z) = x 202.24 x m z - 1
c z -b + x 7.68 z - a
(1)
where: a = filter_pole_register_value/256. b = filter_zero_register_value/256. c = high_frequency_gain_register_value. d = low_frequency_gain_register_value. m = 1 when 48.8 kHz fSW < 97.7 kHz. m = 2 when 97.7 kHz fSW < 195.3 kHz. m = 4 when 195.3 kHz fSW < 390.6 kHz. m = 8 when 390.6 kHz fSW. To go from z-domain to s-domain, plug the following equation into the H(z) equation:
z(s) =
SR1 OUTB OUTD DRIVER
SR2
2 f SW + s 2 f SW - s
SR1 SR2
where fSW is the switching frequency. The digital filter introduces an extra phase delay element into the control loop. The digital filter circuit sends the duty cycle information to the PWM circuit at the beginning of each switching cycle (unlike an analog controller, which makes decisions on the duty cycle information continuously). Therefore, the extra phase delay for phase margin, , introduced by the filter block is
= 180 x (fC/fSW)
DRIVER
ADuM1410
Figure 14. PWM Pin Assignment
where: fC is the crossover frequency. fSW is the switching frequency. At one tenth of the switching frequency, the phase delay is 18. The GUI incorporates this phase delay into its calculations. Two sets of registers allow for two distinct filter responses. The main filter, called the normal mode filter, is controlled by programming Register 0x60 to Register 0x63. The other filter, called the light load mode filter, is controlled by programming Register 0x64 to Register 0x67. The ADP1043A uses the light load mode filter only when the modulation is below the load current threshold (programmed through Register 0x3B).
The PWM and SR outputs all work together. Therefore, when reprogramming more than one of these outputs, it is important to first update all the registers, and then latch the information into the ADP1043A at one time. During reprogramming, the outputs are temporarily disabled. A special instruction is sent to the ADP1043A to ensure that new timing information is programmed simultaneously. This is done by setting Register 0x5D[0] to 1. It is recommended that PWM outputs be disabled when not in use. OUTAUX is an additional PWM output pin; OUTAUX allows an extra PWM signal to be generated at a different frequency from the other six PWM outputs. This signal can be used to drive an extra power converter stage, such as a buck controller located in front of a full-bridge converter. OUTAUX can also be used as a clock reference signal.
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08501-014
OUTA OUTB OUTC OUTD
ADP1043A
SYNCHRONOUS RECTIFICATION
SR1 and SR2 are recommended for use as the PWM control signals when using synchronous rectification. These PWM signals can be set up similarly to the other PWM outputs. The turn-on of these signals can be programmed in two ways. They can either be turned on to their full PWM value immediately, or they can be turned on in a soft start fashion. When turned on in a soft start, the signals ramp up from zero duty cycle to the desired duty cycle. The advantage of ramping the SR signals is to minimize a voltage step that would occur by turning the SR FETs on completely. The advantage of turning the SR signals completely on immediately is that they can help to minimize the voltage transient caused by a load step. Using Register 0x54[1], the SR soft start can be programmed to occur just once, the first time that the SR signals are enabled, or every time that the SR signals are enabled. When programming the ADP1043A to use SR soft start, ensure correct operation of this function by setting the falling edge of SR1 (t10) to a lower value than the rising edge of SR1 (t9) and by setting the falling edge of SR2 (t12) to a lower value than the rising edge of SR2 (t11). The speed of the SR enable is approximately 200 s. This ensures that in case of a load step, the SR signals (and any other PWM outputs that are temporarily disabled) can be turned on quickly enough to prevent damage to the FETs that they are controlling.
MODULATION LIMIT
Using the modulation limit register (Register 0x2E), it is possible to apply a maximum modulation limit and a minimum modulation limit to any PWM signal, thus limiting the modulation range of any PWM. These limits are a percentage of the switching period. If the modulation required is lower than the minimum setting, pulse skipping can be enabled. Following is an example of how to use the modulation limit settings. In this example, the switching cycle period is 4 s and modulation on the t2 edge (falling edge) is enabled. The nominal position of t2 is set to 1.6 s, which is 40% of the 4 s period. The modulation high limit is set to (nominal + 50%). Therefore, the modulation high limit is (40% + 50%) = 90% of the switching cycle period; 90% of 4 s = 3.6 s. The modulation low limit is set to (nominal - 35%). Therefore, the modulation low limit is (40% - 35%) = 5% of the switching cycle period; 5% of 4 s = 0.2 s. The GUI provided with the ADP1043A is recommended for evaluating this feature of the ADP1043A (see Figure 15).
Figure 15. Setting Modulation Limits (Modulation Range Shown by Arrows)
OrFET CONTROL (GATE)
The GATE control signal drives an external OrFET. The OrFET gate control is used to protect against power flow into the power supply from another supply. This ensures that power flows only out of the power supply and that the unit can be hot-swapped. The OrFET circuit can be used only when the ADP1043A is connected to a sense resistor on the low side. The OrFET circuit is not guaranteed for operation with high-side current sensing. The GATE pin is an open-drain, N-channel MOSFET. An external 2.2 k pull-up resistor is recommended. Its output is normally high to keep the OrFET turned off. When the start-up criteria have been achieved, the GATE output is pulled low, allowing the OrFET to turn on. The OrFET turn-on and turnoff thresholds can be individually programmed. The GATE outputs are CMOS levels (0 V to 3.3 V). An external driver is required to turn the OrFET on or off. The OrFET can be turned off by three methods: * * * Fault flag (any fault flag can be programmed to turn off the OrFET) Fast OrFET control circuit Accurate OrFET control circuit
ADAPTIVE DEAD TIME CONTROL
A set of registers called the adaptive dead time (ADT) registers (Register 0x68 to Register 0x6F) allows the dead time between PWM edges to be adapted on-the-fly. The ADP1043A uses the ADT only when the modulation is below the dead time (load current) threshold (programmed in Register 0x68). The Analog Devices software GUI allows the user to easily program the dead time values, and it is recommended that the software be used for that purpose. Each individual PWM rising and falling edge (t1 to t14) can then be programmed to have a specific dead time offset. This offset can be positive or negative. The offset is relative to the nominal edge position. For example, if t1 has a nominal rising edge of 100 ns and the ADT setting for t1 is -15 ns, t1 moves to 85 ns when it falls below the adaptive dead time threshold. The dead times are programmed using Register 0x69 to Register 0x6F.
LIGHT LOAD MODE
Register 0x3B allows the ADP1043A to shut down PWM outputs under light load conditions. The light load current threshold can be programmed. Below this current threshold, the SR outputs are disabled. The user can also program any of the other PWM outputs to shut down below this current threshold. This allows the ADP1043A to be used with an interleaved two transistor forward topology, incorporating phase shedding at light load. The light load mode digital filter is also used during light load mode.
Fast OrFET control looks at the reverse voltage across CS2+ and CS2- and is implemented using an analog comparator (see Figure 16). If the voltage difference between CS2+ and CS2- is greater than the fast OrFET threshold programmed in Register 0x30, the OrFET is turned off.
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08501-015
ADP1043A
Accurate OrFET control also uses the reverse voltage across the CS2+ and CS2- pins to disable the OrFET (see Figure 16). If the voltage difference between CS2+ and CS2- is greater than 0 mV, the OrFET is disabled. The accurate OrFET circuit is more accurate, but it is slower than the fast OrFET circuit. The OrFET turn-on circuit looks at the voltage difference between VS1 and VS2 (see Figure 16). When the forward voltage drop from VS1 to VS2 is greater than the programmable OrFET enable threshold (Register 0x30[5:4]), the OrFET is enabled. The OrFET enable threshold can be set to -0.5%, 0%, 1%, or 2% of the nominal output voltage (12 V).
Recommended Setup
In a 12 V application, while in normal operating mode * * * * When 12 V < VOUT < OVP, use the accurate OrFET control circuit to turn off the OrFET. When VOUT > OVP, use load OVP to turn off the OrFET.
In a 12 V application, while in light load mode When 12 V < VOUT < OVP, use ACSNS to turn off the OrFET. When VOUT > OVP, use load OVP to turn off the OrFET.
In a 12 V application, when an internal short circuit occurs, follow this procedure: 1. 2. Use fast OrFET to turn off the OrFET. Use CS1 OCP or VS1 UVP to shut down the unit and restart it.
12V VOUT 11k 10k 10k 1k
RSENSE DRIVER
11k 1k
CS2-
CS2+
VS1
VS2
GATE
OrFET ENABLE
S R
Q
OrFET ENABLE THRESHOLD REG 0x30[5:4] DIFFERENTIAL TO SINGLEFAST OrFET ENDED FAST OrFET DEBOUNCE COMPARATOR REG 0x30[1] OrFET DISABLE FAST OrFET BYPASS REG 0x30[0]
FAST OrFET THRESHOLD REG 0x30[3:2]
CS2 ADC DIFFERENTIAL TO SINGLEENDED
ACCURATE OrFET DISABLE FLAG ACCURATE OrFET THRESHOLD REG 0x30[7:6]
FLAGS
100A
100A
REG 0x18[15:4]
Figure 16. OrFET Control Circuit Internal Detailed Diagram
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08501-016
CS2 VALUE REGISTER
ADP1043A
OrFET Operation Examples Hot Plug into a Live Bus
A new PSU is plugged into a live 12 V bus (yellow). The internal voltage VS1 (red) is ramped up before the OrFET is turned on. After the OrFET is turned on (green), current in the new PSU begins to flow to the load (blue). The turn-on voltage threshold between the new PSU and the bus is programmable.
VS3
Short Circuit
When one of the output rectifiers fails, the bus voltage can collapse if the OrFET is not promptly turned off. The fast OrFET comparator is used to protect the system from this fault event. Figure 19 shows a short circuit applied to the output capacitors, before the OrFET. After the fast OrFET threshold for CS2 (blue) is triggered, the OrFET (green) is turned off. In this case, the gate driver is not very fast and takes about 500 ns. (A larger buffer to drive the OrFET would turn it off quicker.) Figure 19 also shows the operation when the short circuit is removed. The internal regulation point, VS1 (red), returns to 12 V, and the OrFET (green) is reenabled. The PSU again begins to contribute current to the load (blue).
VS3
VS1
OrFET
4
CS2
3 2 4
OrFET
CS2 CH1 2.00V CH2 2.00V CH3 2.00A CH4 10.0V M10.0ms A CH4 100mV
08501-017
3
Figure 17. Hot Plug into a Live Bus (Yellow Is Bus Voltage; Red Is VS1 Voltage; Green Is OrFET Control Signal; Blue Is Load Current)
VS1
Runaway Master
A rogue PSU on the bus (yellow) has a fault condition, and the result is that the bus voltage increases above the OVP threshold. The good PSU turns off the OrFET (green) and regulates its internal voltage VS1 (red). When the rogue power supply fault condition is removed, the bus voltage decreases. The OrFET of the good PSU is immediately turned on and the good PSU resumes regulating from VS3.
VS3 VS1 CH1 2.00V CH2 2.00V CH3 2.00A CH4 10.0V M200.0ms A CH4 7.5mV
08501-019 08501-020
Figure 19. Internal Short Circuit (Yellow Is Bus Voltage; Red Is VS1 Voltage; Green Is OrFET Control Signal; Blue Is Load Current)
Light Load Mode Operation
PSU 1 increases its voltage at light load from 12 V to 12.1 V (yellow). Both PSU 1 and PSU 2 are CCM, so PSU 1 sources current and PSU 2 sinks current (blue). In PSU 2, after 10 ms the accurate OrFET control turns off the OrFET to prevent reverse current from flowing. Note that the OrFET voltage (green) is solid during this transition because PSU 1 and PSU 2 are in CCM mode.
VS1 VS3
4
OrFET
CS2
3 4
OrFET
CH1 2.00V CH2 2.00V CH3 2.00A CH4 10.0V
M50.0ms
A CH4
0mV
Figure 18. Runaway Master (Yellow Is Bus Voltage; Red Is VS1 Voltage; Green Is OrFET Control Signal; Blue Is Load Current)
08501-018
3
CS2
CH1 2.00V CH2 2.00V CH3 2.00A CH4 10.0V
M5.0ms
A CH4
8.3mV
Figure 20. Light Load Mode (Yellow Is Bus Voltage; Red Is VS1 Voltage; Green Is OrFET Control Signal; Blue Is Load Current)
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ADP1043A
VDD
When VDD is applied, a certain time elapses before the part is capable of regulating the power supply. When the VDD rises above the power-on reset and UVLO levels, it takes approximately 20 s for VCORE to reach its operational point of 2.5 V. The EEPROM contents are then downloaded to the registers. The download takes an additional 25 s (approximately). After the EEPROM download, the ADP1043A is ready for operation. If the ADP1043A is programmed to power up at this time, the soft start ramp begins.
POWER GOOD
The ADP1043A has two power-good pins. The PGOOD1 pin and fault flag are set when any of the following conditions are out of range: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, or load OVP. The PGOOD2 pin and fault flag are set when any flag is set: power supply, OrFET, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, voltage continuity, UVP, accurate OrFET disable, ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local OVP, load OVP, OTP, CRC fault, and EEPROM unlocked. If Register 0x2D[3] is set, PGOOD2 looks only at the flags that are not programmed to be ignored. The PGOOD2 pin can also be used as an interrupt pin to notify a host controller that a flag has been set. The polarity of the PGOOD1 and PGOOD2 pins is configured as active low.
VDD/VCORE OVLO
The ADP1043A has built-in overvoltage protection (OVP) on its supply rails. When the VDD or VCORE voltage rises above the OVLO threshold, the response can be programmed. This circuit can be set to be ignored, but it is recommended that the user not program the OVP circuit to be ignored.
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ADP1043A
SOFT START
A dedicated filter is used during soft start. The filter is disabled at the end of the soft start routine, and the voltage loop digital filter is used. 3. 4. The soft start begins to ramp up the power supply voltage at the start of Time t2. The ADP1043A keeps the OrFET gate signal turned off. The voltage differential across the OrFET increases (VS1 - VS2) due to the diode conduction of the OrFET. When the voltage differential reaches the OrFET enable threshold (Register 0x30, Bits[5:4]), the OrFET gate signal is enabled at Time t3. The ADP1043A begins to regulate voltage from VS3 instead of VS1. After the power supply voltage increases above the VS1 UVP undervoltage limit (Register 0x34, Bits[6:0]), at the end of Time t4, the UVP flag is reset. After the UVP flag is reset and if all other PGOOD1 fault conditions are OK, the PGOOD1 signal waits for Time t5 before it is enabled. The length of t5 is programmable in Register 0x2D, Bits[7:4].
Fault Condition During Soft Start
If a CS1 fast OCP fault condition occurs during soft start, the entire soft start routine is reset, and the ADP1043A begins another soft start routine. All other fault flags are ignored during soft start.
Soft Start Routine
When the user turns on the power supply (enables PSON), the following soft start procedure occurs: 1. The PSON signal is enabled at Time t0. The ADP1043A checks that initial flags are OK. These flags include VDD OK and GND OK. The ADP1043A waits for Time t1 before it begins soft start. The length of t1 is set in Register 0x2C, Bits[4:3].
t0 t1
5.
6.
2.
t3 t2 t4 t5
PSON
SOFT START RAMP UVP
VOUT VOLTAGE 120mV (VS1 - VS2) VOLTAGE
GATE SIGNAL
LOOP CONTROLLED FROM VS1
LOOP CONTROLLED FROM VS3
UVP FLAG
PGOOD1
Figure 21. Soft Start Timing Diagram
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08501-021
ADP1043A
CURRENT SHARING (SHARE)
The ADP1043A supports both analog current sharing and digital current sharing. It is recommended that analog current sharing be used because it offers improved performance over digital current sharing. Digital current sharing requires a load line of >15 m to prevent oscillation between units. The analog current sharing scheme has no such issues. Using Register 0x29, Bit 3, it is possible to program the ADP1043A to use the CS1 current information or the CS2 current information for current sharing. The power supply with the highest current controls the bus (master). A power supply that is putting out less current (slave) sees that another supply is providing more power to the load than it is. During the next cycle, the slave increases its current output contribution by increasing its output voltage. This cycle continues until the slave outputs the same current as the master, within a programmable tolerance range. Figure 22 shows the configuration of the digital share bus.
VDD
Analog Current Sharing
The ADP1043A supports analog current sharing. The current reading from CS1 or CS2 can be output to the SHAREo pin in the form of a digital bit stream, which is the output of the current sense ADC (see Figure 23). The bit stream is proportional to the current being delivered by this unit to the load. By filtering this digital bit stream using an external RC filter, the current information is turned into an analog voltage. This means that there is now an analog voltage that is proportional to the current being delivered by this unit to the load. This voltage can be compared to the share bus. If the unit is not supplying enough current, an error signal can be applied to the VS3 feedback point. This signal causes the unit to increase its output voltage and, therefore, its current contribution to the load. For more information about the analog current share functionality, including schematics and measurements in different fault and setup conditions, see the product page for the ADP1043A.
CURRENT SENSE INFO DIGITAL WORD
SHAREi
SHAREo
POWER SUPPLY A SHARE BUS SHAREi
CURRENT SENSE INFO
DIGITAL WORD
SHAREo
POWER SUPPLY B
Figure 22. Digital Current Share Configuration
The digital share bus is based on a single-wire communication bus principle; that is, the clock and data signals are contained together. When two or more ADP1043A devices are connected, they synchronize their share bus timing. This synchronization is performed by the start bit at the beginning of a communications frame. If a new ADP1043A is hot-swapped onto an existing digital share bus, it waits to begin sharing until the next frame. The new ADP1043A monitors the share bus until it sees a stop bit, which designates the end of a share frame. It then performs synchronization with the other ADP1043A devices during the next start bit. The digital share bus frame is shown in Figure 24.
Digital Share Bus
The digital share bus scheme is similar in principle to the traditional analog share bus scheme. The difference is that instead of using a voltage on the share bus to represent current, a digital word is used. The ADP1043A outputs a digital word onto the share bus. The digital word is a function of the current that the power supply is providing (the higher the current, the larger the digital word).
CURRENT
CS2+
CS2- VOLTAGE
Figure 23. Analog Current Share Configuration
2 STOP BITS (IDLE) START BIT 0 2 STOP BITS (IDLE) START BIT 0 NEXT FRAME FRAME
08501-024
8-BIT DATA
PREVIOUS FRAME
Figure 24. Digital Current Share Frame Timing Diagram
Rev. 0 | Page 20 of 72
08501-022
CURRENT SENSE ADC
BIT STREAM
SHARE BUS
SHAREo BIT STREAM LPF
08501-023
ADP1043A
Figure 25 shows the possible signals on the share bus.
LOGIC 1
Round 1
In Round 1, every supply first places its MSB on the bus. If a supply senses that its MSB is the same as the value on the bus, it continues to Round 2. If a supply senses that its MSB is less than the value on the bus, it means that this supply must be a slave. When a supply becomes a slave, it stops communicating on the share bus because it knows that it is not the master. The supply then increases its output voltage in an attempt to share more current. If two units have the same MSB, they both continue to Round 2, because either of them could be the master.
LOGIC 0
IDLE PREVIOUS BIT
t1
NEXT BIT
08501-025
t0 tBIT
Figure 25. Share Bus High, Low, and Idle Bits
The length of a bit (tBIT) is fixed at 10 s. A Logic 1 is defined as a high-to-low transition at the start of the bit and a low-to-high transition at 75% of tBIT. A Logic 0 is defined as a high-to-low transition at the start of the bit and a low-to-high transition at 25% of tBIT. The bus is idle when it is high during the whole period of tBIT. All other activity on the bus is illegal. Glitches up to tGLITCH (200 ns) are ignored. The digital word that represents the current information is eight bits long. The ADP1043A takes the eight MSBs of the CS1 or CS2 reading (whichever the user chooses as the current share signal) and uses this reading as the digital word. When read, the share bus value at any given time is equal to the CS1 or CS2 current reading (see Figure 26).
Round 2
In Round 2, all supplies that are still communicating on the bus place their second MSB on the share bus. If a supply senses that its MSB is less than the value on the bus, it means that this supply must be a slave and it stops communicating.
Round 3 to Round 8
The same algorithm is repeated for up to eight rounds to allow supplies to compare their digital words and, in this way, to determine whether each unit is the master or a slave.
Digital Share Bus Configuration
The digital share bus can be configured in various ways. The bandwidth of the share bus loop is programmable in Register 0x29[2:0]. The extent to which a slave tries to match the current of the master can be selected by programming Register 0x2A[3:0]. The primary side or the secondary side can be used as the current share signal by programming Register 0x29[3]. A load line may be required between PSUs when using a digital share bus. A minimum impedance of 15 m is recommended between the remote voltage sense node and the load.
Digital Share Bus Scheme
Each power supply compares the digital word that it is outputting with the digital words of all the other supplies on the bus.
PSU A
VDD 8-BIT WORD 0x8F
0x8F MASTER
SHAREi
SHARE BUS
CS2+ IOUT = 35A 1m CS2-
+ 35mV -
2293 DEC 0x8F5 15.26V = 1 LSB
CURRENT SENSE ADC
12-BIT
DIGITAL FILTER /16
8-BIT 143 DEC 0x8F
SHAREo DIGITAL WORD 0x8F 8-BIT WORD
Figure 26. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
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08501-026
35mV/15.26V = 2293
ADP1043A POWER SUPPLY SYSTEM AND FAULT MONITORING
The ADP1043A has extensive system and fault monitoring capabilities. The system monitoring functions include voltage, current, power, and temperature readings. The fault conditions include out-of-limit values for current, voltage, power, and temperature. The limits for the fault conditions are programmable. The ADP1043A has an extensive set of flags that are set when certain thresholds or limits are exceeded. These thresholds and limits are described in the Fault Registers section. In a 12 V system, this equates to
VOUT = (VSx_Voltage_Value/2643) x 12 V
CURRENT READINGS
CS1 Pin DC Input Voltage
The CS1 ADC is identical in design to the VS1, VS2, and VS3 ADCs. Therefore, the description in the Voltage Readings section also applies to the CS1 ADC. When there is exactly 1 V on the CS1 pin, the value in the CS1 value register (Register 0x13) reads 2968. CS1 has an input range of 1.38 V. The ADC performs a 12-bit reading conversion on this value, which means that the LSB size is 1.38 V/4096 = 337 V. The equation to calculate the ADC code at a certain CS1 input voltage (Vx) is given by the following formula:
ADC Code = Vx/337 V
FLAGS
The ADP1043A has an extensive set of flags that are set when certain limits, conditions, and thresholds are exceeded. The real-time status of these flags can be read in Register 0x00 to Register 0x03. The response to these flags is individually programmable. Flags can be ignored or used to trigger tasks such as turning off certain PWM outputs or the OrFET GATE output. Flags can also be used to turn off the power supply. The ADP1043A can be programmed to respond when these flags are reset. For more information, see Register 0x08 to Register 0x0D. The ADP1043A also has a set of latched fault registers (Register 0x04 to Register 0x07). The latched fault registers have the same flags as Register 0x00 to Register 0x03, but the flags in the latched registers remain set so that intermittent faults can be detected. Reading a latched register resets all the flags in that register.
For example, when there is 1 V on the CS1 input pin
ADC Code = 1 V/337 V ADC Code = 2968
AC Input Voltage
CS1 often receives a rectified ac signal through a current transformer. In this case, the ADC has a frequency response (see Figure 27).
105 103
MONITORING FUNCTIONS
The ADP1043A monitors and reports several signals, including voltages, currents, power, and temperature. All these values are stored in individual registers and can be read through the I2C interface. See the Value Registers section for more details.
CS1 ADC FREQUENCY RESPONSE PERCENTAGE DEVIATION (%)
101 99 97 95 93 91 89 87
08501-041
VOLTAGE READINGS
The VS1, VS2, and VS3 ADCs have an input range of 1.55 V. The outputs of the ADCs are 12-bit values, which means that the LSB size is 1.55 V/4096 = 378.4 V. The user is limited to an input range of 1.5 V, which means that the ADC output code is limited to 1.5 V/378.4 V = 3964. The equation to calculate the ADC code at a certain voltage (Vx) is given by the following formula:
ADC Code = Vx/378.4 V
85 1k
10k
100k
CS1 INPUT FREQUENCY (Hz)
For example, when there is 1 V on the input of the ADC
ADC Code = 1 V/378.4 V ADC Code = 2643
Figure 27. CS1 ADC Frequency Response
To compensate for this frequency response, the multiplication factor (M) should be used, as shown in the following equation:
M = (-2 x 10-18 x fSW3) + (2 x 10-12 x fSW2) + (2 x 10-8 x fSW) + 0.9998
In a 12 V application, the 12 V reading is divided down using a resistor divider network to provide 1 V at the sense pin. Therefore, to convert the register value to a real voltage, use the following formula:
VOUT = (VSx_Voltage_Value/2643) x ((R1 + R2)/R2)
where fSW is the switching frequency of the power supply. Using the multiplication factor (M) results in a more accurate reading. This formula can be used by an MCU or other system monitoring device. The ADP1043A GUI has the option to use this formula.
Rev. 0 | Page 22 of 72
ADP1043A
CS2 Pin
The user sets the full-scale (FS) voltage drop--37.5 mV, 75 mV, or 150 mV--that is present across the RSENSE resistor by programming Register 0x23, Bits[7:6]. The CS2 ADC has an input range of 250 mV. The resolution is 12 bits, which means that the LSB size is 250 mV/4096 = 61.04 V. The user is limited to an input range of 215 mV. The equation to calculate the ADC code at a certain voltage (VX) is given by the following formula:
ADC Code = VX/250 mV x 4096
FIRST FLAG FAULT ID AND VALUE REGISTERS
When the ADP1043A registers several fault conditions, it stores the value of the first fault in a dedicated register. For example, if the overtemperature (OTP) fault is registered, followed by an OVP fault, the OTP flag is stored in the first flag ID register (Register 0x10). This register gives the user more information for fault diagnosis than a simple flag. The contents of this register are latched, meaning that they are stored until read by the user. The contents are also reset by a PSON signal. If a flag is set to be ignored, it does not appear in the first flag register.
For example, when there is 150 mV on the input of the ADC
ADC Code = 150 mV/250 mV x 4096 ADC Code = 2457
EXTERNAL FLAG INPUT (FLAGIN PIN)
The FLAGIN pin can be used to send an external fault signal into the ADP1043A. The reaction to this flag can be programmed in the same way as the internal flags.
Therefore, to convert the CS2 value reading to a real current, use the following formula:
IOUT = (CS2_Value/2457) x (FS/RSENSE)
TEMPERATURE READINGS (RTD PIN)
The RTD pin is set up for use with an external 100 k negative temperature coefficient (NTC) thermistor. The RTD pin has an internal 10.8 A current source. Therefore, with a 100 k thermistor, the voltage on the RTD pin is 1 V at 25C. An ADC on the ADP1043A monitors the voltage on the RTD pin.
where: FS is the full-scale voltage drop (37.5 mV, 75 mV, or 150 mV). RSENSE is the sense resistor value. For example, if CS2_Value = 1520, RSENSE = 20 m, and FS = 150 mV, the real current is calculated as follows:
IOUT = (1520/2457) x (150 mV/20 m) IOUT = 4.64 A
10A RTD RTD ADC OTP FLAG FLAGS
08501-027
POWER READINGS
The output power value register (Register 0x19) is the product of the VS3 voltage value and the CS2 current value. Therefore, a combination of the formulas in the Voltage Readings section and the CS2 Pin section is used to calculate the power reading in watts. This register is a 16-bit word. It multiplies two 12-bit numbers and discards the eight LSBs.
POUT = (VOUT) x (IOUT)
100k NTC
RTD TEMPERATURE VALUE REGISTER REG 0x1A[15:4]
OTP THRESHOLD REG 0x2F[7:0]
Figure 28. RTD Pin Internal Details
For example,
POUT = (12 V) x (4.64 A) = 55.68 W
POWER MONITORING ACCURACY
The ADP1043A power monitoring accuracy is specified relative to the full-scale range of the signal that it is measuring.
The output of the RTD ADC is linearly proportional to the voltage on the RTD pin. However, thermistors exhibit a nonlinear function of resistance vs. temperature. Therefore, it is necessary to perform some postprocessing on the RTD ADC reading to accurately read the temperature. This postprocessing can be in the form of a lookup table or polynomial equation to match the specific NTC being used.
OVERTEMPERATURE PROTECTION (OTP)
If the temperature sensed at the RTD pin exceeds the programmable threshold, the OTP flag is set. The hysteresis on this flag is 16 mV (see Register 0x2F in Table 43 for details). The response to the OTP flag is programmable. The RTD trim is required to make accurate temperature readings at the lower end of the RTD ADC range. This results in a more accurate measurement for determining the OTP threshold (see the RTD/OTP Trim section).
Rev. 0 | Page 23 of 72
ADP1043A
OVERCURRENT PROTECTION (OCP)
The ADP1043A has several OCP functions. CS1 and CS2 have individual OCP circuits to provide both primary and secondary side protection. CS1 has two protection circuits: CS1 fast OCP and CS1 accurate OCP (see Figure 29). CS1 fast OCP is an analog comparator. When the voltage at the CS1 pin exceeds the (fixed) 1.2 V threshold, the CS1 fast OCP flag is set. A blanking time can be set to ignore the current spike at the beginning of the current signal. A debounce time can be programmed to improve the noise immunity of the OCP circuit. When the CS1 fast OCP comparator is set, all PWM outputs are immediately disabled for the remainder of the switching cycle. They are reenabled at the start of the next switching cycle. This function can be bypassed if not needed.
VIN OUTA OUTC
CS1 accurate OCP is used for more precise control of overcurrent protection. With CS1 accurate OCP, the reading at the output of the CS1 ADC (Register 0x13) is compared to a programmable OCP value. The CS1 accurate OCP value can be programmed from 0 to 31 decimal using Register 0x22, Bits[4:0]. If the CS1 reading exceeds the CS1 accurate OCP value, the CS1 accurate OCP flag is set. The speed of this decision is 10 ms. The response to the flag is programmable. CS2 has one OCP protection circuit: CS2 accurate OCP. The reading at the output of the CS2 ADC (Register 0x18) is compared to a programmable OCP threshold. The CS2 OCP threshold can be programmed from 0 to 254 decimal using Register 0x26, Bits[7:0]. If the CS2 reading exceeds the CS2 OCP threshold, the CS2 accurate OCP flag is set. The speed of this decision is 10 ms. The response to the flag is programmable.
OUTB
OUTD
CS1
12 ADC CS1 ACCURATE OCP FLAG SHUTDOWN CS1 FAST OCP FLAG FLAGS OUTA OUTB OUTC OUTD SR1 SR2 OUTAUX
08501-028
CS1 ACCURATE OCP SETTING REG 0x22[4:0] 1.2V CS1 FAST OCP BYPASS REG 0x27[4]
FAST OCP COMPARATOR
CS1 FAST OCP BLANKING REG 0x22[7:5]
CS1 FAST OCP DEBOUNCE REG 0x27[7:6]
CYCLE-BY-CYCLE SHUTDOWN
PWM
FLAGIN
Figure 29. CS1 OCP Detailed Internal Schematic
Rev. 0 | Page 24 of 72
ADP1043A
CONSTANT CURRENT MODE
The ADP1043A can be configured to operate in constant current mode. The threshold to enter constant current mode operation is 10% current below the CS2 accurate OCP setting. Below this current, the part operates normally, using the output voltage as the feedback signal for closed-loop operation. When the ADP1043A reaches the constant current mode threshold, a flag is set. The CS2 current reading is used instead of the output voltage as the feedback signal for closed-loop operation. The output voltage is ramped down linearly to 60% of its nominal value as the load resistance decreases to ensure that the current remains constant. When the control loop reaches 60% of VOUT, the part again uses the output voltage to close the loop, but at the reduced level (60% of nominal). If the load resistance continues to decrease, the current may rise again in this region, up to the CS2 OCP level, but the voltage is kept limited to 60% of nominal (see Figure 30). The UVP or CS2 OCP flags can be used to program a shutdown action.
VOUT
OVERVOLTAGE PROTECTION (OVP)
The ADP1043A has two OVP circuits. If the output voltage at the VS1, VS2, or VS3 pin exceeds the programmable threshold for that pin, that OVP flag is set; the response to that flag can be programmed. VS1 has one OVP circuit. VS2 and VS3 share the other OVP circuit. The OVP circuits can be programmed for different OVP thresholds. See Register 0x32 and Register 0x33 for more information. The formula to set the OVP threshold voltage is given by
VSx OVP = [(89 + VS1_OVP_Setting)/128] x 1.55 V
For example, when the VS1 OVP setting = 10, then
VS1 OVP = [(89 + 10)/128] x 1.55 V = 1.2 V
UNDERVOLTAGE PROTECTION (UVP)
If the voltage being sensed at the VS1 pin goes below the programmable UVP threshold, the UVP flag is set. Exceptions to this rule (called undervoltage blanking) include during startup and when ACSNS is not within limits. The response to the UVP condition is programmable (see Register 0x34 in Table 48 for more information).
VOUT NOMINAL
VOUT x 60%
OCP OCP x 90%
Figure 30. Constant Current Mode (VOUT vs. IOUT)
08501-029
IOUT
Rev. 0 | Page 25 of 72
ADP1043A
AC SENSE (ACSNS)
The ACSNS circuit performs multiple monitoring functions. It determines indirectly whether the primary side input voltage is present, as well as monitoring whether a switching waveform is present at the output of the synchronous rectifier stage (or rectifier diodes). The output of the synchronous rectifier stage (or rectifier diodes) is connected to this pin through an external resistor divider network. The ACSNS circuit within the ADP1043A has a comparator that checks for a signal of 0.45 V or greater every switching cycle. For example, if the switching frequency is set to 200 kHz, the switching cycle is 5 s. The comparator timeout is therefore set to 5 s to match the switching cycle. If the comparator does not trip during the 5 s interval, the ACSNS flag is set. Also note that the ADP1043A assumes that the CS1 current pulse signal that it sees first in each cycle is related to OUTB, and that the second current pulse signal in each cycle is related to OUTD. If the first current pulse signal is smaller than the second, OUTB is increased and OUTD is decreased. If the first current pulse signal is greater than the second, OUTB is decreased and OUTD is increased.
LOAD LINE
The ADP1043A can optionally introduce a digital load line into the power supply. This option is programmed in the load line impedance register (Register 0x36). This feature can be used for advanced current sharing techniques. By default, the load line is disabled. The load line is introduced digitally, and its slope can be programmed. It works by taking the CS2 current reading and adjusting the output voltage accordingly. A load line of up to 51.5 m can be chosen. Figure 31 shows the load line results using the ADP1043A evaluation board. The evaluation board uses a 10 m RSENSE resistor.
100
VOLT-SECOND BALANCE
The ADP1043A has a dedicated circuit to maintain volt-second balance in the main transformer when operating in full-bridge topology. This means that a dc blocking capacitor is not necessary. The circuit monitors the dc current flowing in both halves of the full bridge and stores this information. It compensates the PWM drive signals to ensure equal current flow in both halves of the full bridge. The input is through the CS1 pin. Several switching cycles are required for the circuit to operate effectively. The volt-second balance places up to 80 ns of modulation on the OUTB and OUTD pins. Note that the compensation of the PWM drive signals is performed on t4 (OUTB) and t8 (OUTD) only. Therefore, it is necessary to use these pins as the modulating PWM signals for the feature to operate correctly. The SR1 and SR2 rising edges (t9 and t11) can also be independently set to modulate due to the volt-second balance circuit. The SR1 rising edge (t9) modulates in the same direction as the OUTB falling edge (t4); the SR2 rising edge (t11) modulates in the same direction as the OUTD falling edge (t8).
99
VOUT (%)
98 DISABLED SETTING 0 SETTING 1 SETTING 2 SETTING 3 SETTING 4 SETTING 5 SETTING 6 SETTING 7 0 20 40 60 80 100 120
08501-030
97
96
95 RSENSE VOLTAGE DROP (mV)
Figure 31. Load Line Settings
Rev. 0 | Page 26 of 72
ADP1043A POWER SUPPLY CALIBRATION AND TRIM
The ADP1043A allows the entire power supply to be calibrated and trimmed digitally in the production environment. It can calibrate items such as output voltage and trim for tolerance errors introduced by sense resistors and resistor dividers, as well as its own internal circuitry. The part comes factory trimmed, but it can be retrimmed by the user to compensate for the errors introduced by external components. The ADP1043A allows the user enough trim capability to trim for external components with a tolerance of 0.5% or better. If the ADP1043A is not trimmed in the production environment, it is recommended that components with a 0.1% tolerance be used for the inputs to CS1, CS2, VS1, VS2, VS3+, and VS3- to meet data sheet specifications.
CS2 Offset Trim
It is important to perform the CS2 offset trim as described in the following steps. 1. 2. 3. Set the nominal full-scale sense resistor voltage drop in Register 0x23, Bits[7:6]. Set high-side or low-side current sensing in Register 0x24, Bit 7. Offset errors can be introduced by the external bias resistors and the internal current sources. Apply no-load current across the sense resistor. Adjust the CS2 offset trim value (Register 0x24, Bits[6:0]) until the CS2 value in Register 0x18 reads as close to 100 decimal as possible. Adjust the CS2 digital trim register (Register 0x25) until the CS2 value in Register 0x18 reads 0.
4.
CS1 TRIM
Using a DC Signal
A known voltage (Vx) is applied at the CS1 pin. The CS1 ADC should output a digital code equal to Vx/337 V. The CS1 gain trim register (Register 0x21) is adjusted until the CS1 ADC value in Register 0x13 reads the correct digital code.
The offset trim is now completed, and the ADC code reads 0 if there is no-load current across the sense resistor.
CS2 Gain Trim
After performing the offset trim, perform the gain trim to remove any mismatch that is introduced by the sense resistor tolerance. The ADP1043A can trim for sense resistors with a tolerance of 1% or better. 1. 2. Apply a known current (IOUT) across the sense resistor. Adjust the CS2 gain trim value (Register 0x23, Bits[5:0]) until the CS2 value in Register 0x18 reads the value calculated by the following formula:
CS2 Value = IOUT x 2457 x (RSENSE/FS)
Using an AC Signal
A known current (Ix) is applied to the PSU input. This current passes through a current transformer, a diode rectifier, and an external resistor (RCS1) to convert the current information to a voltage (Vx). This voltage is fed into the CS1 pin. The voltage (Vx) is calculated as follows:
Vx = Ix x (n2/n1) x RCS1
where n2/n1 is the turns ratio of the current transformer. The CS1 ADC should output a digital code equal to Vx/337 V. The CS1 gain trim register (Register 0x21) is adjusted until the CS1 ADC value in Register 0x13 reads the correct digital code. As described in the CS1 Pin section, the CS1 ADC has a frequency response. To achieve more accurate trimming, the following multiplication factor (M) should be used:
M = (-2 x 10-18 x fSW3) + (2 x 10-12 x fSW2) + (2 x 10-8 x fSW) + 0.9998
where: FS is the full-scale voltage drop. RSENSE is the sense resistor value. For example, if IOUT = 4.64 A, RSENSE = 20 m, and FS = 150 mV, then
CS2 Value = (4.64 A x 2457) x (20 m/150 mV) CS2 Value = 1520 decimal
where fSW is the switching frequency of the power supply.
The CS2 circuit is now trimmed. After the current sense trim is performed, the OCP limits and settings should be configured.
CS2 TRIM
The CS2 trim must compensate for offset and gain errors. The offset error requires both an analog trim and a digital trim. The CS2 ADC range does not begin at 0 V but instead begins at -25 mV to allow it to perform reverse current protection for the OrFET circuit. Therefore, with -25 mV at the CS2 input, the ADC code should read 0. With 0 mV at the CS2 input, the ADC code should read 100 decimal. For this reason, the analog offset trim is performed until the CS2 reading equals 100 decimal (not 0). For this reason, also, the digital trim is required.
VOLTAGE CALIBRATION AND TRIM
The voltage sense inputs are optimized for sensing signals at 1 V and cannot sense a signal greater than 1.5 V. In a 12 V system, a 12:1 resistor divider is required to reduce the 12 V signal to below 1.5 V. It is recommended that the output voltage of the power supply be reduced to 1 V for best performance. The resistor divider can introduce errors, which need to be trimmed. The ADP1043A has enough trim range to trim out errors introduced by resistors with 0.5% tolerance or better. The ADCs output a digital word of 2643 decimal (0xA53) when there is exactly 1 V at their inputs.
Rev. 0 | Page 27 of 72
ADP1043A
OUTPUT VOLTAGE SETTING (VS3+, VS3- TRIM)
The VS3 input requires a gain trim. Enable the power supply with no-load current. The power supply output voltage is divided down by the VS3 resistor divider to give 1 V at the VS3+ and VS3- input pins. The VS3 trim register (Register 0x3A) is altered until the VS3 value in Register 0x17 reads 2643 decimal (0xA53). This step should be done before any other trim routines.
CS2 + and CS2-
The routing of the traces from the sense resistor to the ADP1043A should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible.
VS3+ and VS3-
The routing of the traces from the remote voltage sense point to the ADP1043A should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible.
VS1 TRIM
The VS1 input requires a gain trim. Enable the power supply with no-load current. The VS1 voltage is divided down by the VS1 resistor divider to give 1 V at the VS1 pin. The VS1 trim register (Register 0x38) is altered until the VS1 value in Register 0x15 reads 2643 decimal (0xA53).
VDD
Place decoupling capacitors as close to the part as possible. A 100 nF capacitor from VDD to AGND is recommended.
VS2 TRIM
The VS2 input requires a gain trim. Enable the power supply with no-load current. The VS2 voltage is divided down by the VS2 resistor divider to give 1 V at the VS2 pin. The VS2 trim register (Register 0x39) is altered until the VS2 value in Register 0x16 reads 2643 decimal (0xA53).
SDA and SCL
The routing of the traces should be laid out in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible.
CS1
Run the traces from the current sense transformer to the ADP1043A in parallel to each other. The traces should also be kept close together and as far from the switch nodes as possible.
RTD/OTP TRIM
A 100 k NTC thermistor should be used with the ADP1043A. In a PSU trim, the following procedure should be used: 1. 2. Heat the thermistor or PSU to a known temperature that will result in an OTP threshold. Adjust the temperature gain trim register (Register 0x2B) to give the correct temperature reading (Register 0x1A) at this temperature. Adjust the OTP threshold register (Register 0x2F) until the OTP flag is set.
Exposed Pad
The exposed pad underneath the ADP1043A should be soldered to the PCB ground plane.
VCORE
Place the 100 nF capacitor as close to the part as possible.
3.
RES
Place the 49.9 k resistor as close to the part as possible.
This procedure achieves the most accurate OTP, because it takes into account the part-to-part variations of the ADP1043A and the thermistor being used.
RTD
Route a single trace to the ADP1043A from the thermistor. Place the thermistor close to the hottest part of the power supply.
LAYOUT GUIDELINES
This section explains best practices that should be followed to ensure optimal performance of the ADP1043A. In general, all components should be placed as close to the ADP1043A as possible. Several inputs to the ADP1043A are sensitive. Therefore, take extra care when handling and soldering the part. Along with correct cleaning of the IC after soldering, a short curing process (1 hour at 150C) is recommended. Analog Devices also recommends encapsulating the IC in protective resin after this curing to ensure that any impurities cannot contaminate the IC.
AGND
Create an AGND ground plane and make a single point (star) connection to the power supply system ground.
Rev. 0 | Page 28 of 72
ADP1043A COMMUNICATION
I2C INTERFACE
Control of the ADP1043A is carried out via the I C interface. The ADP1043A is connected to the I2C bus as a slave device under the control of a master device.
2
I2C Address
The I2C address of the ADP1043A is set by connecting an external resistor from the ADD pin to AGND. Table 5 lists the recommended resistor values and the associated I2C addresses. Eight different addresses can be used. If an incorrect resistor value is used and the resulting I2C address is close to a threshold between two addresses, a flag is set (address flag in Register 0x03, Bit 5; see Table 11). The recommended values in Table 5 can vary by 2 k; the ADP1043A still reports the same address. Therefore, it is recommended that 1% tolerance resistors be used on the ADD pin. I2C Address 0x58 is the broadcast address, which allows multiple parts to be written to simultaneously. By using the broadcast address instead of a specific I2C address from Table 5, all ADP1043A devices on the I2C bus are written to. The broadcast address can be used for write commands only.
Table 5. Recommended Resistor Values for I2C Addresses
I2C Address 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 Resistor Value (k) 9 (or connect the ADD pin directly to AGND) 27 45 63 81 98 116 134 (or connect the ADD pin directly to VDD)
2.
3.
4.
5.
General I2C Timing
The ADP1043A has a timeout feature to protect against a fault condition on the SDA line. The I2C interface monitors the SDA line and, if it stays low for time 0.65 ms < t_low < 1.3 ms, the I2C interface is reset and waits for another start condition. The I2C specification defines specific conditions for different types of read and write operations. General I2C read and write operations are shown in the timing diagrams of Figure 32, Figure 33, and Figure 34, and are described in this section. The general I2C protocol operates as follows: 1. The master initiates a data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. 6.
This indicates that a data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master writes to the slave device. If the R/W bit is a 1, the master reads from the slave device. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-tohigh transition when the clock is high may be interpreted as a stop signal. If the operation is a write operation, the first data byte after the slave address is a command byte that tells the slave device what to expect next. It may be an instruction, such as telling the slave device to expect a block write, or it may be a register address that tells the slave where subsequent data is to be written. Because data can flow in only one direction, as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before a read operation, it may be necessary to first perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device releases the SDA line during the low period before the ninth clock pulse, but the slave device does not pull it low. This is known as a no acknowledge bit. The master takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition.
If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.
Rev. 0 | Page 29 of 72
ADP1043A
1 SCL 9 1 9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADP1043A
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADP1043A
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
08501-031
ACK. BY ADP1043A FRAME 3 DATA BYTE
STOP BY MASTER
Figure 32. Writing a Register Address to the Address Pointer Register, and Then Writing Data to the Selected Register
1 SCL
9
1
9
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 33. Writing to the Address Pointer Register Only
1 SCL
9
1
9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADP1043A
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY ADP1043A STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADP1043A
Figure 34. Reading Data from a Previously Selected Register
Rev. 0 | Page 30 of 72
08501-033
08501-032
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADP1043A
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADP1043A STOP BY MASTER
ADP1043A
EEPROM
The EEPROM is partitioned into two major blocks: the factory block and the main block. The factory block contains 128 8-bit bytes, and the main block contains 8k 8-bit bytes.
Main Block, Page 0 (User Settings)
The ADP1043A user register settings are stored in Page 0 of the main block. Every time that VDD is applied to the ADP1043A, the register settings are automatically downloaded from Page 0 of the EEPROM to the registers. The ADP1043A has a unique command to write new values to Page 0. This is done by writing 0x00 to Register 0x7B. Clicking the Update EEPROM button in the Analog Devices software GUI also performs this task.
Factory Block
The factory block is organized into 128 bytes. It is used to store the original Analog Devices factory calibration and register settings. The user cannot change these settings. The contents of the factory block can be downloaded to the registers at any time by writing 0x01 to Register 0x7B.
MAIN Block, Page 1 to Page 15 (Scratchpad)
Page 1 to Page 15 of the main block can be used as a scratchpad to store other data. Register 0x7C and Register 0x7D are used to point to the page, row, and column of the byte to be accessed.
Main Block
The main block is available to store data. It is partitioned into 16 pages; each page contains 512 bytes. The data on each page is sorted into bytes organized in the form of eight rows and 64 columns (see Figure 35).
PAGE 0 TO PAGE 15 ROW 0 ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW 6 ROW 7 BYTE 0 BYTE 0 BYTE 0 BYTE 0 BYTE 0 BYTE 0 BYTE 0 BYTE 0 COLUMN 0 BYTE 1 BYTE 1 BYTE 1 BYTE 1 BYTE 1 BYTE 1 BYTE 1 BYTE 1 COLUMN 1 BYTE 2 BYTE 2 BYTE 2 BYTE 2 BYTE 2 BYTE 2 BYTE 2 BYTE 2 COLUMN 2 ... ... ... ... ... ... ... ... ... BYTE 62 BYTE 62 BYTE 62 BYTE 62 BYTE 62 BYTE 62 BYTE 62 BYTE 62 COLUMN 62 BYTE 63 BYTE 63
Write Example
Write data 0xAA to Page 12, Row 3, Column 30 of the ADP1043A at I2C Address 0x57.
Write: DevAddr=0x57 AddrPtr=0x7C Data=0x63 Write: DevAddr=0x57 AddrPtr=0x7D Data=0x1E Write: DevAddr=0x57 AddrPtr=0x7E Data=0xAA
Read Example
BYTE 63 BYTE 63 BYTE 63 BYTE 63 BYTE 63 BYTE 63 COLUMN 63
08501-034
Read data from Page 10, Row 7, Column 62 of the ADP1043A at I2C Address 0x50.
Read: DevAddr=0x50 Read: DevAddr=0x50 Read: DevAddr=0x50 AddrPtr=0x7C Data=0x57 AddrPtr=0x7D Data=0x3E AddrPtr=0x7E
Figure 35. EEPROM Page Diagram
Table 6. EEPROM Registers
Address (Hex) 0x5E 0x7B Register Name Password lock EEPROM restore factory default register settings Description Write the password to this register twice to unlock the EEPROM or to change its password Write a command code to this register to perform one of the following EEPROM operations: 0x00: Upload registers to Page 0 of the main block (user settings) 0x01: Download factory settings (factory block) to the registers 0x02: Page erase operation Set XADR[6:0] of EEPROM: XADR[6:3] selects one of 16 pages of the main block XADR[2:0] selects one of eight rows per page Set YADR[5:0] of EEPROM: YADR[5:0] selects one of 64 bytes in a single row Read or write to this register to read or program a byte in EEPROM main memory
0x7C
EEPROM X address
0x7D 0x7E
EEPROM Y address EEPROM register
Rev. 0 | Page 31 of 72
ADP1043A
EEPROM Password Lock
The EEPROM password prevents the EEPROM contents from being changed accidentally or purposely by an unwanted source. The password ensures that critical specifications such as OVP and OCP cannot be changed. The EEPROM is always locked. When the EEPROM downloads its contents to the registers, the password is also downloaded. If the user writes the same password to Register 0x5E twice, the EEPROM is unlocked and can be updated. While the EEPROM is unlocked, it is possible to change the password by writing a new value to Register 0x5E. After this value is updated, the EEPROM contains the new password. The factory default password is 0x00. To update the EEPROM password, the user must write to Register 0x7B. Writing 0x00 to this register updates the EEPROM. The user must wait at least 50 ms after this write command before attempting any further communication with the ADP1043A. Note that the EEPROM should not be written to for the first 500 ms after VDD has been applied.
Cyclic Redundancy Check (CRC)
The ADP1043A performs a check to ensure that the EEPROM contents are correctly downloaded to registers at startup. It compares the total number of 1s downloaded with the total number of 1s that were last written to the EEPROM. If there is a discrepancy, the CRC fault flag is set in Register 0x03, Bit 1. This flag is used to ensure that the correct data is downloaded from the EEPROM to the registers at startup.
SOFTWARE GUI
A free software GUI is available for programming and configuring the ADP1043A. The GUI is designed to be intuitive to power supply designers and dramatically reduces power supply design and development time. The software includes filter design and power supply PWM topology windows. The GUI is also an information center, displaying the status of all readings, monitoring, and flags on the ADP1043A. For more information about the GUI, contact Analog Devices for the latest software and a user guide. Evaluation boards are also available by contacting Analog Devices. To download the latest GUI, click on the About button at the top of the GUI Main screen. Click on the link to check for GUI updates.
EEPROM Password Change
To change the EEPROM password, follow these steps: 1. 2. 3. 4. 5. 6. 7. Write the old password to Register 0x5E (password lock register). Write the new password to Register 0x5E (password lock register) for the first time. Write the new password to Register 0x5E (password lock register) for the second time. Write the new password to Register 0x5E (password lock register) for the third time. Write 0x00 to Register 0x7B. Wait 50 ms. To lock the EEPROM, write any value other than the password value into Register 0x5E.
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ADP1043A REGISTER LISTING
Table 7. Register List
Address Name Fault Registers 0x00 Fault Register 1 0x01 Fault Register 2 0x02 Fault Register 3 0x03 Fault Register 4 0x04 Latched Fault Register 1 0x05 Latched Fault Register 2 0x06 Latched Fault Register 3 0x07 Latched Fault Register 4 0x08 Fault Configuration Register 1 0x09 Fault Configuration Register 2 0x0A Fault Configuration Register 3 0x0B Fault Configuration Register 4 0x0C Fault Configuration Register 5 0x0D Fault Configuration Register 6 0x0E Flag configuration 0x0F Soft start blank fault flags Value Registers 0x10 First flag ID 0x11 Reserved 0x12 VS1/PWM value (input voltage) 0x13 CS1 value (input current) 0x14 CS1 x (VS1/PWM) value (input power) 0x15 VS1 voltage value 0x16 VS2 voltage value 0x17 VS3 voltage value (output voltage) 0x18 CS2 value (output current) 0x19 CS2 x VS3 value (output power) 0x1A RTD temperature value 0x1D Share bus value 0x1E Modulation value 0x1F Line impedance value 0x20 Reserved Current Sense and Current Limit Registers 0x21 CS1 gain trim 0x22 CS1 accurate OCP limit 0x23 CS2 gain trim 0x24 CS2 analog offset trim 0x25 CS2 digital trim 0x26 CS2 accurate OCP limit 0x27 CS1 fast OCP setting 0x28 Volt-second balance gain setting 0x29 Share bus bandwidth 0x2A Share bus setting 0x2B Temperature gain trim 0x2C PSON/soft start setting 0x2D Pin polarity setting 0x2E Modulation limit 0x2F OTP threshold 0x30 OrFET Address Name Voltage Sense Registers 0x31 VS3 voltage setting (remote voltage) 0x32 VS1 overvoltage limit (OVP) 0x33 VS2 and VS3 overvoltage limit (OVP) 0x34 VS1 undervoltage limit (UVP) 0x35 Line impedance limit 0x36 Load line impedance 0x38 VS1 trim 0x39 VS2 trim 0x3A VS3 trim 0x3B Light load mode disable setting ID Registers 0x3C Silicon revision ID 0x3D Manufacturer ID 0x3E Device ID PWM and Synchronous Rectification Timing Registers 0x3F OUTAUX switching frequency setting 0x40 PWM switching frequency setting 0x41 OUTA rising edge timing (OUTA pin) 0x42 OUTA rising edge setting (OUTA pin) 0x43 OUTA falling edge timing (OUTA pin) 0x44 OUTA falling edge setting (OUTA pin) 0x45 OUTB rising edge timing (OUTB pin) 0x46 OUTB rising edge setting (OUTB pin) 0x47 OUTB falling edge timing (OUTB pin) 0x48 OUTB falling edge setting (OUTB pin) 0x49 OUTC rising edge timing (OUTC pin) 0x4A OUTC rising edge setting (OUTC pin) 0x4B OUTC falling edge timing (OUTC pin) 0x4C OUTC falling edge setting (OUTC pin) 0x4D OUTD rising edge timing (OUTD pin) 0x4E OUTD rising edge setting (OUTD pin) 0x4F OUTD falling edge timing (OUTD pin) 0x50 OUTD falling edge setting (OUTD pin) 0x51 SR1 rising edge timing (SR1 pin) 0x52 SR1 rising edge setting (SR1 pin) 0x53 SR1 falling edge timing (SR1 pin) 0x54 SR1 falling edge setting (SR1 pin) 0x55 SR2 rising edge timing (SR2 pin) 0x56 SR2 rising edge setting (SR2 pin) 0x57 SR2 falling edge timing (SR2 pin) 0x58 SR2 falling edge setting (SR2 pin) 0x59 OUTAUX rising edge timing (OUTAUX pin) 0x5A OUTAUX rising edge setting (OUTAUX pin) 0x5B OUTAUX falling edge timing (OUTAUX pin) 0x5C OUTAUX falling edge setting (OUTAUX pin) 0x5D OUTx and SRx pin disable setting 0x5E Password lock
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ADP1043A
Address Name Digital Filter Programming Registers 0x5F Soft start digital filter LF gain setting 0x60 Normal mode digital filter LF gain setting 0x61 Normal mode digital filter zero setting 0x62 Normal mode digital filter pole setting 0x63 Normal mode digital filter HF gain setting 0x64 Light load mode digital filter LF gain setting 0x65 Light load mode digital filter zero setting 0x66 Light load mode digital filter pole setting 0x67 Light load mode digital filter HF gain setting Adaptive Dead Time Registers 0x68 Dead time threshold 0x69 Dead Time 1 0x6A Dead Time 2 0x6B Dead Time 3 0x6C Dead Time 4 0x6D Dead Time 5 0x6E Dead Time 6 0x6F Dead Time 7 EEPROM Registers 0x7B EEPROM restore factory default register settings 0x7C EEPROM X address 0x7D EEPROM Y address 0x7E EEPROM register
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ADP1043A DETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS
Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also note that these register bits are cleared when read via the I2C interface unless the fault is still present. It is recommended that the latched fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00--Fault Register 1 and Register 0x04--Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Bits 7 6 5 Name Power supply OrFET PGOOD1 fault R/W R R R Description 1 = power supply is off. All PWM outputs are disabled. This bit stays high until the power supply is restarted. 1 = OrFET control signal at the GATE pin (Pin 16) is off. 1 = Power-Good 1 fault. At least one of the following flags has been set: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, or load OVP. 1 = Power-Good 2 fault. At least one of the following flags has been set: power supply, OrFET, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, voltage continuity, UVP, accurate OrFET disable, ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local OVP, load OVP, OTP, CRC fault, and EEPROM unlocked. (The user can choose to ignore one or more flags. See Table 41 for more information.) Sync rects are disabled. This flag is set when one of the following cases is true: SR1 and SR2 are disabled by the user. The load current has fallen below the threshold in Register 0x3B. A flag that was configured to disable the sync rects has been set. CS1 current is above its fast overcurrent protection limit. This is a 1.2 V threshold on the CS1 pin. Fast OCP is a comparator. CS1 current is above its accurate overcurrent protection limit. CS2 current is above its accurate overcurrent protection limit. Register Action None
0x30 None
4
PGOOD2 fault
R
0x2D
None
3
SR off
R
None 0x5D 0x3B 0x08 to 0x0D Programmable 0x22 0x26 Programmable Programmable
2 1 0
CS1 fast OCP CS1 accurate OCP CS2 accurate OCP
R R R
Table 9. Register 0x01--Fault Register 2 and Register 0x05--Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Bits 7 Name Voltage continuity UVP Accurate OrFET disable VDD UV VCORE OV VDD OV Load OVP Local OVP R/W R Description Voltage differential between VS1 and VS2 pins or between VS2 and VS3 pins is outside limits. Either (VS1 - VS2) > 100 mV or (VS2 - VS3) > 100 mV. VS1 is below its undervoltage limit. Reverse voltage across CS2 pins is above limit. This is the accurate OrFET reverse voltage. VDD is below limit. 2.5 V VCORE is above limit. VDD is above limit. The I2C interface stays functional, but a PSON toggle is required to restart the power supply. VS2 or VS3 is above its overvoltage limit. VS1 is above its overvoltage limit. Register Action Programmable
6 5 4 3 2 1 0
R R R R R R R
0x34 0x30
Programmable Programmable Immediate shutdown Immediate shutdown Programmable Programmable Programmable
0x0E 0x33 0x32
Table 10. Register 0x02--Fault Register 3 and Register 0x06--Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)
Bits 7 6 5 4 3 2 1 0 Name OTP Reserved Share bus Constant current Reserved Line impedance Soft start filter External flag R/W R R R R R R R R Description Temperature is above OTP limit. Reserved. Current share is outside regulation limit. Power supply is operating in constant current mode (constant current mode is enabled). Reserved. Line impedance between VS2 and VS3 is above limit. The soft start filter is in use. The external flag pin (FLAGIN) is set.
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Register 0x2F 0x2A 0x27
Action Programmable Programmable None
0x35 0x5F
None None Programmable
ADP1043A
Table 11. Register 0x03--Fault Register 4 and Register 0x07--Latched Fault Register 4 (1 = Fault, 0 = Normal Operation)
Bits 7 6 5 4 3 2 1 0 Name Reserved Modulation Address Light load mode Reserved ACSNS CRC fault EEPROM unlocked R/W R R R R R R R R Description Reserved. Modulation is at its minimum or maximum limit. The ADD resistor is not correct. The system is in light load mode. Reserved. The ac sense timing or amplitude is not correct. The ac sense comparator has not tripped for one switching cycle. The EEPROM contents downloaded are incorrect. The EEPROM is unlocked. Register 0x2E 0x3B Action None None None Programmable Immediate shutdown None
Table 12. Register 0x08 to Register 0x0D--Fault Configuration Registers
Register Name Fault Configuration Register 1 Fault Configuration Register 2 Fault Configuration Register 3 Fault Configuration Register 4 Fault Configuration Register 5 Fault Configuration Register 6 Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D Bits [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] [7:4] [3:0] Flag CS1 fast OCP CS1 accurate OCP CS2 accurate OCP Load OVP (VS2 or VS3) Local OVP (VS1) External flag input (FLAGIN) OTP UVP Accurate OrFET reverse voltage Voltage continuity Share bus ACSNS Shutdown Debounce See Register 0x27 in Table 35 See Register 0x0E in Table 14 See Register 0x0E in Table 14 2 ms 2 ms 100 ms 100 ms 100 ms 100 ms 100 ms 100 ms 1 ms or 100 ms
Register 0x08 to Register 0x0D allow the user to program the response when each flag is set.
Table 13. Register 0x08 to Register 0x0D--Fault Configuration Register Bit Descriptions
Bits 7 Name Timing R/W R/W Description This bit specifies when the flag is set. 0 = after debounce. 1 = immediately. This bit specifies when the part is reenabled after the fault that triggered the flag has been resolved. 0 = reenable after the power supply reenable time set in Register 0x0E[1:0]. 1 = remain disabled; power supply must be restarted to reenable. These bits specify the action that the part takes in response to the flag. Bit 5 Bit 4 Action 0 0 Ignore flag completely 0 1 Disable SR1 and SR2 1 0 Disable OrFET 1 1 Disable power supply (disable all PWM outputs and OrFET GATE) Same as Bit 7. Same as Bit 6. Same as Bits[5:4].
6
Resolve issue
R/W
[5:4]
Action
R/W
3 2 [1:0]
Timing Resolve issue Action
R/W R/W R/W
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ADP1043A
Table 14. Register 0x0E--Flag Configuration Register
Bits 7 6 Name VDD OV/VCORE OV flags ignore VDD OV/VCORE OV restart VDD OV/VCORE OV debounce Accurate OCP off delay for CS1 and CS2 R/W R/W R/W Description Setting this bit means that the VDD OV and VCORE OV flags are ignored. Setting this bit to 1 means that if the part shuts down, it will download the EEPROM contents again before restarting. Setting this bit to 0 means that if the part shuts down, it will not download the EEPROM contents again before restarting. Setting this bit to 1 means that there is a 500 s debounce before the part shuts down. Setting this bit to 0 means that there is a 2 s debounce before the part shuts down. When an accurate OCP flag is set, there is a delay before the corresponding action is performed. This delay is programmed using these bits. Bit 4 Bit 3 Bit 2 Debounce 0 0 0 1.3 ms 0 0 1 13 ms 0 1 0 130 ms 0 1 1 260 ms 1 0 0 600 ms 1 0 1 1.3 sec 1 1 0 2 sec 1 1 1 2.6 sec These bits specify the time delay before restarting the power supply after a shutdown. SR1, SR2, and OrFET are reenabled immediately. Bit 1 Bit 0 Time (sec) 0 0 0.5 0 1 1 1 0 2 1 1 4
5 [4:2]
R/W R/W
[1:0]
Power supply reenable time
R/W
Table 15. Register 0x0F--Soft Start Blank Fault Flags Register
Bits 7 6 5 4 3 2 1 0 Name Blank SR Blank OTP Blank FLAGIN Blank local OVP Blank load OVP Blank CS2 accurate OCP Blank CS1 accurate OCP Blank CS1 fast OCP R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit means that the SR1 and SR2 PWM outputs are not enabled until the end of the soft start ramp time. Setting this bit means that the OTP flag is ignored until the end of the soft start ramp time. Setting this bit means that the FLAGIN flag is ignored until the end of the soft start ramp time. Setting this bit means that the local OVP flag is ignored until the end of the soft start ramp time. Setting this bit means that the load OVP flag is ignored until the end of the soft start ramp time. Setting this bit means that the CS2 accurate OCP flag is ignored until the end of the soft start ramp time. Setting this bit means that the CS1 accurate OCP flag is ignored until the end of the soft start ramp time. Setting this bit means that the CS1 fast OCP flag is ignored until the end of the soft start ramp time.
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ADP1043A
VALUE REGISTERS
Table 16. Register 0x10--First Flag ID
Bits [7:4] [3:0] Name Reserved First flag ID R/W R R Description Reserved. These bits record the flag that was set first. Restarting the power supply resets this register. Reading this register also resets the register. Bit 3 Bit 2 Bit 1 Bit 0 Flag Error 0 0 0 0 None No flag 0 0 0 1 Register 0x01, Bit 3 VCORE OV 0 0 1 0 Register 0x01, Bit 2 VDD OV 0 0 1 1 Register 0x03, Bit 1 EEPROM CRC 0 1 0 0 Register 0x00, Bit 2 CS1 fast OCP 0 1 0 1 Register 0x00, Bit 1 CS1 accurate OCP 0 1 1 0 Register 0x00, Bit 0 CS2 accurate OCP 0 1 1 1 Register 0x01, Bit 1 Load OVP 1 0 0 0 Register 0x01, Bit 0 Local OVP 1 0 0 1 Register 0x02, Bit 0 FLAGIN 1 0 1 0 Register 0x02, Bit 7 OTP 1 0 1 1 Register 0x01, Bit 6 UVP 1 1 0 0 Register 0x01, Bit 5 Reverse voltage 1 1 0 1 Register 0x01, Bit 7 Voltage continuity 1 1 1 0 Register 0x02, Bit 5 Share bus 1 1 1 1 Register 0x03, Bit 2 ACSNS
Table 17. Register 0x12--VS1/PWM Value (Input Voltage)
Bits [15:0] Name Input voltage value R/W R Description This register contains the 16-bit input voltage information. Because the input voltage is normally on the other side of the isolation barrier from the ADP1043A, the part does not directly sense the input voltage. The input voltage is defined as the VS1 voltage divided by the PWM modulation. To read the input voltage information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the input voltage information. The eight bits of the second read return the eight LSBs of the input voltage information. To translate this reading into the real input voltage, use the following equation: VINPUT = (Input_Voltage_Value_Reading/2643) x ((R1 + R2)/R2) where R1 and R2 are the external resistor divider values between the power supply output and the VS1 pin. This reading does not take into account an external turns ratio on the main transformer.
Table 18. Register 0x13--CS1 Value (Input Current)
Bits [15:4] Name Input current value R/W R Description This register contains the 12-bit input current information. This value is derived from a voltage measurement at the CS1 input. To read the input current information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the input current information. The top four bits of the second read return the four LSBs of the input current information. The range of the CS1 input pin is from 0 V to 1.38 V. This value has 12 bits of resolution, which results in an LSB size of 337 V. At 0 V input, the value in this register is 0 (0x000). At 1.3 V input, the value in this register is 3856 (0xF10). The nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2968 (0xB98). Reserved.
[3:0]
Reserved
R
Table 19. Register 0x14--CS1 x (VS1/PWM) Value (Input Power)
Bits [15:0] Name Input power value R/W R Description This register contains the 16-bit input power information. This value is the product of the input voltage (VS1/PWM) multiplied by the input current (CS1), that is, (VS1/PWM) x CS1. To read the input power information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the input power information. The eight bits of the second read return the eight LSBs of the input power information.
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ADP1043A
Table 20. Register 0x15--VS1 Voltage Value
Bits [15:4] Name VS1 voltage value R/W R Description This register contains the 12-bit local output voltage information. This voltage is measured at the VS1 pin. To read the VS1 voltage information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the local output voltage information. The top four bits of the second read return the four LSBs of the local output voltage information. The range of the VS1 input pin is from 0 V to 1.55 V. This value has 12 bits of resolution, which results in an LSB size of 378 V. At 0 V input, the value in this register is 0 (0x000). At 1.5 V input, the ADC output is 3964 (0xF7C). The recommended nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Reserved.
[3:0]
Reserved
R
Table 21. Register 0x16--VS2 Voltage Value
Bits [15:4] Name VS2 voltage value R/W R Description This register contains the 12-bit load output voltage information. This voltage is measured at the VS2 pin. To read the load VS2 voltage information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the load output voltage information. The top four bits of the second read return the four LSBs of the load output voltage information. The range of the VS2 input pin is from 0 V to 1.55 V. This value has 12 bits of resolution, which results in an LSB size of 378 V. At 0 V input, the value in this register is 0 (0x000). At 1.5 V input, the ADC output is 3964 (0xF7C). The recommended nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Reserved.
[3:0]
Reserved
R
Table 22. Register 0x17--VS3 Voltage Value (Output Voltage)
Bits [15:4] Name VS3 voltage value R/W R Description This register contains the 12-bit remote output voltage information. This value is the differential voltage between the VS3+ and VS3- pins. To read the remote output voltage information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the remote output voltage information. The top four bits of the second read return the four LSBs of the remote output voltage information. The range of the VS3 input pin is from 0 V to 1.55 V. This value has 12 bits of resolution, which results in an LSB size of 378 V. At 0 V input, the value in this register is 0 (0x000). At 1.5 V input, the ADC output is 3964 (0xF7C). The recommended nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Reserved.
[3:0]
Reserved
R
Table 23. Register 0x18--CS2 Value (Output Current)
Bits [15:4] Name Output current value R/W R Description This register contains the 12-bit output current information. This information is the voltage drop across the sense resistor. The user must divide this value by the sense resistor value to obtain the current value. To read the output current information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the output current information. The top four bits of the second read return the four LSBs of the output current information. The CS2 pin has an input range of 250 mV. This value has 12 bits of resolution, which results in an LSB size of 61.04 V. The nominal voltage setting in Bits[7:6] of Register 0x23 changes this LSB step size. If the nominal voltage range is from 75 mV to 150 mV, the LSB step size is 61.04 V. At a 30 mV input signal on CS2, the value in this register is 30 mV/61.04 V = 491 (0x1EB). If the nominal voltage range is from 37.5 mV to 75 mV, the LSB step size is 30.52 V. At a 30 mV input signal on CS2, the value in this register is 30 mV/30.52 V = 982 (0x3D6). If the nominal voltage range is from 0 mV to 37.5 mV, the LSB step size is 15.26 V. At a 30 mV input signal on CS2, the value in this register is 30 mV/15.26 V = 1966 (0x7AE). Reserved.
[3:0]
Reserved
R
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ADP1043A
Table 24. Register 0x19--CS2 x VS3 Value (Output Power)
Bits [15:0] Name Output power value R/W R Description This register contains the 16-bit output power information. This value is the product of the remote output voltage value (VS3) and the output current reading (CS2). To read the output power information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the output power information. The eight bits of the second read return the eight LSBs of the output power information. See the Power Readings section for the formulas needed to convert this digital reading into power information.
Table 25. Register 0x1A--RTD Temperature Value
Bits [15:4] Name Temperature value R/W R Description This register contains the 12-bit output temperature information, as determined from the RTD pin. To read the temperature information, this register must be read using two consecutive read operations. The eight bits of the first read return the eight MSBs of the temperature information. The top four bits of the second read return the four LSBs of the temperature information. The range of the RTD pin is from 0 V to 1.55 V. This value has 12 bits of resolution, which results in an LSB size of 378 V. At 0 V input, the value in this register is 0 (0x000). At 1.5 V input, the ADC output is 3964 (0xF7C). The recommended nominal voltage at this pin is 1 V. At 1 V input, the value in this register is 2643 (0xA53). Reserved.
[3:0]
Reserved
R
Table 26. Register 0x1D--Share Bus Value
Bits [7:0] Name Share bus value R/W R Description This register contains the 8-bit share bus voltage information. If the power supply is the master, this register outputs 0.
Table 27. Register 0x1E--Modulation Value
Bits [7:0] Name Modulation value R/W R Description This register contains the 8-bit modulation information. It outputs the amount of modulation from 0% to 100% that is being placed on the modulating edges.
Table 28. Register 0x1F--Line Impedance Value
Bits [7:0] Name Line impedance value R/W R Description This register contains the 8-bit line impedance information. This value is (VS2 - VS3)/CS2.
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ADP1043A
CURRENT SENSE AND CURRENT LIMIT REGISTERS
Table 29. Register 0x21--CS1 Gain Trim
Bits 7 [6:0] Name Gain polarity CS1 gain trim R/W R/W R/W Description 1 = negative gain is introduced. 0 = positive gain is introduced. This value calibrates the primary side current sense gain. See the CS1 Trim section for more information.
Table 30. Register 0x22--CS1 Accurate OCP Limit
Bits [7:5] Name CS1 fast OCP blanking R/W R/W Description These bits determine the blanking time for CS1 before fast OCP is enabled. This time is measured from the start of a switching cycle. It is synchronized with the rising edge of OUTB and OUTD. If using OUTAUX, the time is synchronized with the rising edge of OUTAUX. Bit 7 Bit 6 Bit 5 Delay (ns) 0 0 0 0 0 0 1 40 0 1 0 80 0 1 1 120 1 0 0 200 1 0 1 400 1 1 0 600 1 1 1 800 These bits set the CS1 accurate OCP threshold. The digital word that is output from the CS1 ADC is compared with this threshold. If the CS1 ADC reading (Register 0x13) is greater than the OCP threshold set by these bits, the CS1 accurate OCP flag is set. This value should be programmed only after the CS1 trim has been performed. The range of these bits is from 0 to 31, that is, 0 V to 1.38 V in 43.125 mV steps. The following equation gives the threshold of the CS1 OCP: CS1_OCP_Threshold = (CS1_OCP_Limit/31) x 1.38 The range is programmable from 0% to 138% of the nominal voltage on the CS1 pin. For example, if the CS1 OCP limit is 12 V, then CS1_OCP_Threshold = (12/31) x 1.38 V = 534 mV Setting these bits to 0 gives an OCP limit of 0% of the nominal voltage on the CS1 pin. Setting these bits to 10 gives an OCP limit of 44.5% of the nominal voltage on the CS1 pin. Setting these bits to 31 gives an OCP limit of 138% of the nominal voltage on the CS1 pin.
[4:0]
CS1 accurate OCP
R/W
Table 31. Register 0x23--CS2 Gain Trim
Bits [7:6] Name CS2 nominal R/W R/W Description These bits set the nominal full-scale voltage drop across the sense resistor. This is Step 1 in the CS2 Offset Trim section. These bits set the LSB step size of the CS2 ADC. Nominal Voltage Drop LSB Step Size (V) Bit 7 Bit 6 Across RSENSE at Full Scale (mV) 0 0 37.5 15.26 0 1 75 30.52 1 0 150 61.04 1 = negative gain is introduced. 0 = positive gain is introduced. This register calibrates the secondary side (CS2) current sense gain. It calibrates for errors in the sense resistor. This is Step 2 in the CS2 Gain Trim section.
5 [4:0]
Gain polarity CS2 gain trim
R/W R/W
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ADP1043A
Table 32. Register 0x24--CS2 Analog Offset Trim
Bits 7 6 [5:0] Name CS2 high side Offset polarity CS2 offset trim R/W R/W R/W R/W Description This bit is set high if high-side current sensing is used. This bit is set low if low-side current sensing is used. This is Step 2 in the CS2 Offset Trim section. 1 = negative offset is introduced. 0 = positive offset is introduced. This register calibrates the secondary side (CS2) current sense common-mode error. It calibrates for errors in the resistor divider network. This is Step 3 in the CS2 Offset Trim section.
Table 33. Register 0x25--CS2 Digital Trim
Bits [7:0] Name CS2 digital trim R/W R/W Description This register contains the CS2 digital trim level. This value is used to calibrate the CS2 value that is read in Register 0x18. This is Step 4 in the CS2 Offset Trim section.
Table 34. Register 0x26--CS2 Accurate OCP Limit
Bits [7:0] Name CS2 accurate OCP R/W R/W Description This register sets the CS2 accurate OCP current level. This 8-bit number is compared to the CS2 value register (Register 0x18). When the CS2 value register is greater than the value in this register, the CS2 accurate OCP flag is set. The maximum setting of this register is 254 (0xFE). Setting this register to 255 (0xFF) is not allowed.
Table 35. Register 0x27--CS1 Fast OCP Setting
Bits [7:6] Name CS1 fast OCP debounce R/W R/W Description These bits set the CS1 fast OCP debounce value. This is the minimum time that the CS1 signal must be constantly above the fast OCP limit before the PWM outputs are shut down. When this happens, all PWM outputs are disabled for the remainder of the switching cycle. Bit 7 Bit 6 Debounce (ns) 0 0 0 0 1 40 1 0 80 1 1 120 Setting this bit enables volt-second balance for the main transformer (used for full-bridge configurations). This value introduces extra modulation on the OUTB and OUTD modulating waveforms to provide volt-second balance in both branches of the full bridge. For more information, see the Volt-Second Balance section. Setting this bit to 1 means that the FLAGIN pin is used for CS1 fast OCP instead of the CS1 pin. When this bit is set, constant current mode is enabled 10% below the CS2 accurate OCP limit. 1 = constant current mode enabled. 0 = constant current mode disabled. Setting this bit means that the current spike at the beginning of each CS1 reading is ignored by the volt-second balance circuit. If the CS1 fast OCP comparator is set, all PWM outputs that are on during that time are immediately disabled for the remainder of the switching cycle. The PWM outputs resume normal operation at the beginning of the next switching cycle. These bits set the number of consecutive switching cycles for the comparator before the CS1 fast OCP flag is set. Bit 1 Bit 0 Number of Switching Cycles 0 0 1 0 1 2 1 0 4 1 1 8
5
VS balance enable
R/W
4 3
CS1 fast OCP bypass Constant current mode VS balance leading edge blanking CS1 fast OCP timeout
R/W R/W
2 [1:0]
R/W R/W
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ADP1043A
Table 36. Register 0x28--Volt-Second Balance Gain Setting
Bits [7:2] [1:0] Name Reserved VS balance gain setting R/W R/W R/W Description Reserved. These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor of 64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance. When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance. Bit 1 Bit 0 Volt-Second Balance Gain 0 0 1 0 1 4 1 0 16 1 1 64
Table 37. Register 0x29--Share Bus Bandwidth
Bits [7:5] 4 Name Reserved Bit stream R/W R/W R/W Description Reserved. 1 = the current sense ADC reading is output on the SHAREo pin. This bit stream can be used for analog current sharing. 0 = the digital share bus signal is output on the SHAREo pin. This signal can be used for digital current sharing. 1 = CS1 reading used for current share. 0 = CS2 reading used for current share. These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is the lowest possible bandwidth, and the value 111 is the highest possible bandwidth.
3 [2:0]
Current share select Share bus bandwidth
R/W R/W
Table 38. Register 0x2A--Share Bus Setting
Bits [7:4] [3:0] Name Number of bits dropped by master Bit difference between master and slave R/W R/W R/W Description These bits determine how much a master device reduces its output voltage to maintain current sharing. These bits determine how closely a slave tries to match the current of the master device. The higher the setting, the larger the distance that satisfies the current sharing criteria.
Table 39. Register 0x2B--Temperature Gain Trim
Bits [7:5] 4 [3:0] Name Reserved Gain polarity Gain trim R/W R/W R/W R/W Description Set these bits to 000 for normal operation. 1 = negative gain is introduced. 0 = positive gain is introduced. This register calibrates the RTD ADC gain. It calibrates for errors in the ADC. This value allows 12% trim to be realized.
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ADP1043A
Table 40. Register 0x2C--PSON/Soft Start Setting
Bits [7:6] Name PS_ON setting R/W R/W Description These bits determine which signal is used by the ADP1043A as the PS_ON control. Bit 7 Bit 6 PS_ON Setting 0 0 The ADP1043A is always on. 0 1 Hardware PSON pin is used to enable or disable the power supply. 1 0 Software PS_ON bit (Bit 5) is used to enable or disable the power supply. 1 1 Both software PS_ON bit and hardware PSON pin must be enabled before the ADP1043A is enabled. Software PS_ON bit. 0 = power supply off. 1 = power supply on. These bits set the time from when the PS_ON control signal is set to when the soft start begins. Bit 4 Bit 3 Delay (sec) 0 0 0 0 1 0.5 1 0 1 1 1 2 If the soft stop feature is enabled, a soft stop occurs even if a fault flag causes a shutdown event. This may cause the ADP1043A to continue switching for longer than desired. The user needs to consider this factor before enabling the soft stop feature. 1 = soft stop time is the same as the soft start time. 0 = no active discharge time. The ADP1043A shuts down the PWM outputs immediately. These bits set the soft start ramp time, that is, the amount of time that it takes for the power supply to reach its nominal value. Bit 1 Bit 0 Ramp Time 0 0 360 s 0 1 10 ms 1 0 20 ms 1 1 40 ms
5
PS_ON
R/W
[4:3]
PS_ON delay
R/W
2
Soft stop enable
R/W
[1:0]
Soft start
R/W
Table 41. Register 0x2D--Pin Polarity Setting
Bits [7:4] Name PGOOD1 on/off debounce R/W R/W Description These bits set the debounce time before the PGOOD1 pin is enabled or disabled. At startup, PGOOD1 is not enabled until a period of time after the following signals are all within normal limits: power supply, CS1 fast OCP, CS1 accurate OCP, CS2 accurate OCP, UVP, local OVP, and load OVP. When PSON is disabled, there is a debounce before PGOOD1 is disabled. Bit 7 Bit 6 Bit 5 Bit 4 Delay Time (ms) 0 0 0 0 320 0 1 0 1 200 1 0 1 0 600 1 1 1 1 0 0 = any flag can set the PGOOD2 pin. 1 = any flag that has not been configured to be ignored can set the PGOOD2 pin. This bit sets the polarity of the FLAGIN input pin: 1 = inverted (low = on). This bit sets the polarity of the OrFET GATE control pin: 1 = inverted (low = on). This bit sets the polarity of the PSON input pin: 1 = inverted (low = on).
3 2 1 0
PGOOD2 flags FLAGIN polarity GATE polarity PSON polarity
R/W R/W R/W R/W
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ADP1043A
Table 42. Register 0x2E--Modulation Limit
Bits 7 Name Full bridge R/W R/W Description Enable this bit when operating in full-bridge mode. This mode distributes the modulation equally between two PWM outputs instead of one. It affects the modulation high limit and the modulation low limit settings. These bits set the maximum allowed modulation that is applied to a PWM output. The value is a percentage of the switching period. Bit 6 Bit 5 Bit 4 Limit (%) Limit (%) in Full-Bridge Mode 0 0 0 Nominal + 12.5% Nominal + 6.25% 0 0 1 Nominal + 25% Nominal + 12.5% 0 1 0 Nominal + 31.25% Nominal + 15.625% 0 1 1 Nominal + 37.5% Nominal + 18.75% 1 0 0 Nominal + 43.75% Nominal + 21.875% 1 0 1 Nominal + 46.88% Nominal + 23.44% 1 1 0 Nominal + 48.44% Nominal + 24.22% 1 1 1 Nominal + 50% Nominal + 25% Reserved. Setting this bit enables pulse skipping mode. If the ADP1043A requires a duty cycle lower than the modulation low limit, pulse skipping is enabled. These bits set the minimum allowed modulation that is applied to a PWM output. The value is a percentage of the switching period. If the modulation calculated is lower than this limit, pulse skipping can be enabled. Bit 1 Bit 0 Limit (%) Limit (%) in Full-Bridge Mode 0 0 Nominal - 50% Nominal - 25% 0 1 Nominal - 48.44% Nominal - 24.22% 1 0 Nominal - 46.88% Nominal - 23.44% 1 1 Nominal - 43.75% Nominal - 21.875%
[6:4]
Modulation high limit
R/W
3 2 [1:0]
Reserved Pulse skipping Modulation low limit
R/W R/W
Table 43. Register 0x2F--OTP Threshold
Bits [7:0] Name OTP threshold R/W R/W Description The OTP threshold value is compared to the RTD ADC reading (Register 0x1A). If the RTD ADC reading is lower than the threshold set in this register, the OTP flag is set. (The flag is set below the threshold because using an NTC thermistor causes the reading to decrease as the temperature increases.) Each LSB typically corresponds to an increased OTP threshold of 3.04 mV. The RTD ADC range is 0 V to 1.55 V; the OTP threshold is 9.12 mV to 760 mV. There is a hysteresis of 16 mV on the OTP flag. ... Bit 7 Bit 6 Bit 3 Bit 2 Bit 1 Bit 0 OTP Limit (mV) 0 0 ... 0 0 1 1 9.12 0 0 ... 0 1 0 0 12.16 0 0 ... 0 1 0 1 15.20 ... ... ... ... ... ... ... ... 1 1 ... 1 0 0 1 756.96 1 1 ... 1 0 1 0 760
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ADP1043A
Table 44. Register 0x30--OrFET
Bits [7:6] Name Accurate OrFET threshold R/W R/W Description These bits program the voltage difference between CS2+ and CS2- at which the accurate OrFET flag is set. The CS2+ and CS2- input pins are used to control this function. Bit 7 Bit 6 Voltage Drop Across Sense Resistor from CS2+ to CS2- (Threshold) 0 0 0 mV 0 1 Reserved 1 0 Reserved 1 1 Reserved These bits program the voltage difference between VS1 and VS2 before the OrFET is enabled. The VS1 and VS2 input pins are used to control the OrFET enable function. Voltage Difference from VS1 to VS2 % of ADC Full Range 12 V VOUT (mV) 48 V VOUT (mV) Bit 5 Bit 4 0 0 -0.5 -93 -372 0 1 0 0 0 1 0 1 186 744 1 1 2 372 1488 These bits program the threshold voltage difference between CS2+ and CS2- at which the OrFET is disabled. The CS2+ and CS2- input pins are used to control this function. The internal circuit is an analog comparator. Bit 3 Bit 2 Voltage Difference from CS2+ to CS2- (mV) 0 0 -100 0 1 -75 1 0 -50 1 1 -25 These bits determine the debounce on the fast OrFET control before it disables the OrFET. 0 = 40 ns. 1 = 200 ns. Set this bit to completely bypass the fast OrFET control. To also bypass the accurate OrFET disable control, the response to the accurate OrFET disable flag should be set to ignore.
[5:4]
OrFET enable threshold
R/W
[3:2]
Fast OrFET threshold
R/W
1
Fast OrFET debounce Fast OrFET bypass
R/W
0
R/W
VOLTAGE SENSE REGISTERS
Table 45. Register 0x31--VS3 Voltage Setting (Remote Voltage)
Bits [7:0] Name VS3 voltage setting R/W R/W Description This register is used to set the output voltage (voltage differential at the VS3+ and VS3- pins). Programmable from 0% to 155% of nominal voltage. Each LSB corresponds to a 0.6% increase. Setting this register to a value of 0xA5 gives an output voltage setting of 100% of the nominal voltage. This is the default value and is stored in this register when shipped from the factory. Updating the VS3 voltage setting is a two-stage process. First, the user must change the value in this register; this information is stored in a shadow register. To latch the new VS3 voltage setting into the state machine, the user must set the GO bit (Register 0x5D[0]).
Table 46. Register 0x32--VS1 Overvoltage Limit (OVP)
Bits [7:3] Name VS1 OVP setting R/W R/W Description Local overvoltage limit. This limit is programmable from 107.7% to 145.3% of the nominal VS1 voltage; 0x00 corresponds to 107.7%. Each LSB results in an increase of 1.21%. The VS1 OVP threshold is calculated as follows: VS1_OVP_Threshold = [(89 + VS1_OVP_Setting)/128] x 1.55 V For example, if the VS1 OVP setting is 10, then VS1_OVP_Threshold = [(89 + 10)/128] x 1.55 V = 1.2 V Setting these bits to 0 gives an OVP limit of 107.7% of the nominal VS1 voltage. Setting these bits to 10 gives an OVP limit of 120% of the nominal VS1 voltage. Setting these bits to 20 gives an OVP limit of 132% of the nominal VS1 voltage. Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS1 voltage. Reserved.
Rev. 0 | Page 46 of 72
2
Reserved
R/W
ADP1043A
Bits [1:0] Name OVP sampling R/W R/W Description The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP threshold. This OVP flag sampling period is 80 s. The number of samples can be increased using these bits. If the number of samples is increased, the average voltage must be greater than the OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average voltage must be greater than the OVP threshold for both cycles. Bit 1 Bit 0 Additional Sampling (s) 0 0 0 (one sample sets the OVP flag) 0 1 80 (two samples set the OVP flag) 1 0 160 (three samples set the OVP flag) 1 1 240 (four samples set the OVP flag)
Table 47. Register 0x33--VS2 and VS3 Overvoltage Limit (OVP)
Bits [7:3] Name VS2 and VS3 OVP setting R/W R/W Description Load overvoltage limit. This limit is programmable from 107.7% to 145.3% of the nominal VS2 or VS3 voltage; 0x00 corresponds to 107.7%. Each LSB results in an increase of 1.21%. The VS2/VS3 OVP threshold is calculated as follows: VSx_OVP_Threshold = [(89 + VSx_OVP_Setting)/128] x 1.55 V For example, if the VS3 OVP setting is 10, then VS3_OVP_Threshold = [(89 + 10)/128] x 1.55 V = 1.2 V Setting these bits to 0 gives an OVP limit of 107.7% of the nominal VS2/VS3 voltage. Setting these bits to 10 gives an OVP limit of 120% of the nominal VS2/VS3 voltage. Setting these bits to 20 gives an OVP limit of 132% of the nominal VS2/VS3 voltage. Setting these bits to 31 gives an OVP limit of 145.3% of the nominal VS2/VS3 voltage. When this bit is set, the ADP1043A regulates from the VS3 node at all times. When this bit is not set, the ADP1043A uses the VS1 voltage as the regulating point during soft start and when the OrFET is disabled. The OVP flag is set if the average voltage during the OVP sampling period is greater than the OVP threshold. This OVP flag sampling period is 80 s. The number of samples can be increased using these bits. If the number of samples is increased, the average voltage must be greater than the OVP threshold for each of those cycles. For example, if this value is set to two cycles, the average voltage must be greater than the OVP threshold for both cycles. Bit 1 Bit 0 Additional Sampling (s) 0 0 0 (one sample sets the OVP flag) 0 1 80 (two samples set the OVP flag) 1 0 160 (three samples set the OVP flag) 1 1 240 (four samples set the OVP flag)
2
Regulating point
R/W
[1:0]
OVP sampling
R/W
Table 48. Register 0x34--VS1 Undervoltage Limit (UVP)
Bits 7 Name End of cycle shutdown R/W R/W Description This bit is valid only when the OUTAUX pin is used for regulation. When any flag shuts down the power supply, the OUTAUX PWM is immediately shut down. This bit specifies when the other PWM outputs are shut down. 1: All other PWM outputs are shut down at the end of the switching cycle. 0: All other PWM outputs are immediately shut down. These bits set the UVP limit to one of 128 settings. The UVP limit can be programmed from 0% to 155% of the nominal VS1 voltage. Each LSB increases the voltage by 155%/128 = 1.21%. In reality, there are 82 usable settings, which program the UVP threshold from 0% to 100% of the nominal VS1 voltage. The VS1 UVP threshold is calculated as follows: VS1_UVP_Threshold = [(VS1_UVP_Setting)/128] x 1.55 V For example, if the VS1 UVP setting is 60, then VS1_UVP_Threshold = [60/128] x 1.55 V = 726 mV Setting these bits to 0 gives a UVP limit of 0% of the nominal VS1 voltage. Setting these bits to 66 (0x42) gives a UVP limit of 80% of the nominal VS1 voltage. Setting these bits to 82 (0x52) gives a UVP limit of 100% of the nominal VS1 voltage. Setting these bits to 127 (0x7F) gives a UVP limit of 155% of the nominal VS1 voltage.
[6:0]
VS1 UVP setting
R/W
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ADP1043A
Table 49. Register 0x35--Line Impedance Limit
Bits [7:0] Name Line impedance limit R/W R/W Description This value sets the threshold at which the line impedance flag is enabled. This 8-bit value is compared with the line impedance value (Register 0x1F). If the line impedance value exceeds this value, the line impedance flag is set (Register 0x02, Bit 2).
Table 50. Register 0x36--Load Line Impedance
Bits [7:4] 3 [2:0] Name Reserved Enable Load line R/W R/W R/W R/W Description Reserved. Set this bit to enable the load line. This value specifies how much the output voltage decreases from nominal at full load. Bit 2 Bit 1 Bit 0 Impedance Setting Equivalent Load Line (m) 0 0 0 Setting 7 51.5 0 0 1 Setting 6 26 0 1 0 Setting 5 12.5 0 1 1 Setting 4 6.25 1 0 0 Setting 3 3 1 0 1 Setting 2 1.5 1 1 0 Setting 1 0.7 1 1 1 Setting 0 0
Table 51. Register 0x38--VS1 Trim
Bits 7 [6:0] Name Trim polarity VS1 trim R/W R/W R/W Description 1 = negative gain is introduced. 0 = positive gain is introduced. These bits set the amount of gain trim that is applied to the VS1 ADC reading. This register trims the voltage at the VS1 pin for external resistor tolerances. When there is 1 V on the VS1 pin, this register is trimmed until the VS1 voltage value register (Register 0x15) reads 2643 (0xA53).
Table 52. Register 0x39--VS2 Trim
Bits 7 [6:0] Name Trim polarity VS2 trim R/W R/W R/W Description 1 = negative gain is introduced. 0 = positive gain is introduced. These bits set the amount of gain trim that is applied to the VS2 ADC reading. This register trims the voltage at the VS2 pin for external resistor tolerances. When there is 1 V on the VS2 pin, this register is trimmed until the VS2 voltage value register (Register 0x16) reads 2643 (0xA53).
Table 53. Register 0x3A--VS3 Trim
Bits 7 [6:0] Name Trim polarity VS3 trim R/W R/W R/W Description 1 = negative gain is introduced. 0 = positive gain is introduced. These bits set the amount of gain trim that is applied to the VS3 ADC reading. This register trims the voltage at the VS3 pins for external resistor tolerances. When there is 1 V on each VS3 pin, this register is trimmed until the VS3 voltage value register (Register 0x17) reads 2643 (0xA53). The VS3 trim must be performed before the load OVP and load UVP trims are performed.
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ADP1043A
Table 54. Register 0x3B--Light Load Mode Disable Setting
Bits 7 6 5 4 3 [2:0] Name Disable OUTAUX Disable OUTD Disable OUTC Disable OUTB Disable OUTA Light load SR disable R/W R/W R/W R/W R/W R/W R/W Description Setting this bit means that OUTAUX is also disabled if the load current drops below the light load SR disable threshold. Setting this bit means that OUTD is also disabled if the load current drops below the light load SR disable threshold. Setting this bit means that OUTC is also disabled if the load current drops below the light load SR disable threshold. Setting this bit means that OUTB is also disabled if the load current drops below the light load SR disable threshold. Setting this bit means that OUTA is also disabled if the load current drops below the light load SR disable threshold. These bits set the load current limit on the CS2 ADC below which the synchronous rectifier outputs (SR1 and SR2) are disabled. This value also determines the point at which the power supply goes into light load mode. Below this limit, the light load mode filter registers are used. Above this limit, the normal mode filter registers are used. This value is programmable from 0 mV to 46 mV of the CS2 ADC. The hysteresis on this signal is 8 mV. The settings for Bits[2:0] are shown in terms of the voltage across the CS2 pins, as well as the percentage of load current for the different nominal CS2 settings. Threshold for Each Nominal CS2 Setting (mV) Bit 2 Bit 1 Bit 0 % of Full Load 37.5 mV Setting 75 mV Setting 150 mV Setting 0 0 0 0 0 0 0 0 0 1 4 1.5 3 6 0 1 0 8.5 3.1 6.3 12.5 0 1 1 13 4.9 9.8 19.5 1 0 0 18 6.6 13.3 26.5 1 0 1 22 8.3 16.5 33 1 1 0 26 9.8 19.5 39 1 1 1 30 11.5 23 46
ID REGISTERS
Table 55. Register 0x3C--Silicon Revision ID
Bits [7:0] Name Silicon revision R/W R Description This register contains the manufacturer's silicon revision code for the device. This value is used by the manufacturer for test purposes and should not be read from in normal operation.
Table 56. Register 0x3D--Manufacturer ID (Power-On Default: 0x41)
Bits [7:0] Name Manufacturer ID code R/W R Description This register contains the manufacturer's ID code for the device. It is used by the manufacturer for test purposes and should not be read from in normal operation. This value is hardwired to 0x41 to represent the Analog Devices ID code.
Table 57. Register 0x3E--Device ID (Power-On Default: 0x43)
Bits [7:0] Name Device ID code R/W R Description This register contains the ID code for the device. This value is hardwired to 0x43 to represent the ADP1043A.
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ADP1043A
PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS
Figure 36 and Table 58 to Table 88 describe the implementation and programming of the seven PWM signals that are output from the ADP1043A. In general, it is recommended that t1 be set to 0 and that t1 be set as the reference point for the other signals.
t2
PWM1 (OUTA)
t1 t4
PWM2 (OUTB)
t3 t5
PWM3 (OUTC)
t6 t8
PWM4 (OUTD)
t7
SYNC RECT 1 (SR1)
t10 t9
SYNC RECT 2 (SR2)
t12 t11
PWM5 (OUTAUX)
t13
08501-035
t14 tPERIOD tPERIOD
Figure 36. PWM Timing Diagram
Table 58. Register 0x3F--OUTAUX Switching Frequency Setting
Bits [7:6] [5:0] Name Reserved Switching frequency R/W R/W R/W Description Reserved. This register sets the switching frequency of the OUTAUX signal. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0
Rev. 0 | Page 50 of 72
Frequency (kHz) 48.8 50.4 52.0 53.8 55.8 57.9 60.1 62.5 65.1 67.9 71.0 74.4 78.1 82.2 86.8 91.9 97.6 100.8 104.1 107.7 111.6
ADP1043A
Bits [5:0] Name Switching frequency R/W R/W Description Bit 5 Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 Bit 2 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 Bit 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Frequency (kHz) 115.7 120.2 125.0 130.2 135.8 142.0 148.8 156.2 164.5 173.6 183.8 195.3 201.6 208.3 215.5 223.2 231.5 240.4 250 260 271 284 297 312 328 347 367 390 416 446 480 521 568 625
Table 59. Register 0x40--PWM Switching Frequency Setting
Bits [7:6] [5:0] Name Reserved Switching frequency R/W R/W R/W Description Reserved. This register sets the switching frequency of all the PWM pins other than the OUTAUX pin. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Frequency (kHz) 0 0 0 0 0 0 48.8 0 0 0 0 0 1 50.4 0 0 0 0 1 0 52.0 0 0 0 0 1 1 53.8 0 0 0 1 0 0 55.8 0 0 0 1 0 1 57.9 0 0 0 1 1 0 60.1 0 0 0 1 1 1 62.5 0 0 1 0 0 0 65.1 0 0 1 0 0 1 67.9
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ADP1043A
Bits [5:0] Name Switching frequency R/W R/W Description Bit 5 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 Bit 2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frequency (kHz) 71.0 74.4 78.1 82.2 86.8 91.9 97.6 100.8 104.1 107.7 111.6 115.7 120.2 125.0 130.2 135.8 142.0 148.8 156.2 164.5 173.6 183.8 195.3 201.6 208.3 215.5 223.2 231.5 240.4 250 260 271 284 297 312 328 347 367 390 416 446 480 521 568 625 Resonant mode
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ADP1043A
Table 60. Register 0x41--OUTA Rising Edge Timing (OUTA Pin)
Bits [7:0] Name t1 R/W R/W Description This register contains the eight MSBs of the 12-bit t1 time. This value is always used with the top four bits of Register 0x42, which contains the four LSBs of the t1 time. Each LSB corresponds to 5 ns resolution.
Table 61. Register 0x42--OUTA Rising Edge Setting (OUTA Pin)
Bits [7:4] Name t1 R/W R/W Description These bits contain the four LSBs of the 12-bit t1 time. This value is always used with the eight bits of Register 0x41, which contains the eight MSBs of the t1 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t1 edge. 0 = no PWM modulation of the t1 edge. 1 = negative sign. Increase of PWM modulation moves t1 right. 0 = positive sign. Increase of PWM modulation moves t1 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t1 sign Reserved
R/W R/W R/W
Table 62. Register 0x43--OUTA Falling Edge Timing (OUTA Pin)
Bits [7:0] Name t2 R/W R/W Description This register contains the eight MSBs of the 12-bit t2 time. This value is always used with the top four bits of Register 0x44, which contains the four LSBs of the t2 time. Each LSB corresponds to 5 ns resolution.
Table 63. Register 0x44--OUTA Falling Edge Setting (OUTA Pin)
Bits [7:4] Name t2 R/W R/W Description These bits contain the four LSBs of the 12-bit t2 time. This value is always used with the eight bits of Register 0x43, which contains the eight MSBs of the t2 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t2 edge. 0 = no PWM modulation of the t2 edge. 1 = negative sign. Increase of PWM modulation moves t2 right. 0 = positive sign. Increase of PWM modulation moves t2 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t2 sign Reserved
R/W R/W R/W
Table 64. Register 0x45--OUTB Rising Edge Timing (OUTB Pin)
Bits [7:0] Name t3 R/W R/W Description This register contains the eight MSBs of the 12-bit t3 time. This value is always used with the top four bits of Register 0x46, which contains the four LSBs of the t3 time. Each LSB corresponds to 5 ns resolution.
Table 65. Register 0x46--OUTB Rising Edge Setting (OUTB Pin)
Bits [7:4] Name t3 R/W R/W Description These bits contain the four LSBs of the 12-bit t3 time. This value is always used with the eight bits of Register 0x45, which contains the eight MSBs of the t3 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t3 edge. 0 = no PWM modulation of the t3 edge. 1 = negative sign. Increase of PWM modulation moves t3 right. 0 = positive sign. Increase of PWM modulation moves t3 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t3 sign Reserved
R/W R/W R/W
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ADP1043A
Table 66. Register 0x47--OUTB Falling Edge Timing (OUTB Pin)
Bits [7:0] Name t4 R/W R/W Description This register contains the eight MSBs of the 12-bit t4 time. This value is always used with the top four bits of Register 0x48, which contains the four LSBs of the t4 time. Each LSB corresponds to 5 ns resolution.
Table 67. Register 0x48--OUTB Falling Edge Setting (OUTB Pin)
Bits [7:4] Name t4 R/W R/W Description These bits contain the four LSBs of the 12-bit t4 time. This value is always used with the eight bits of Register 0x47, which contains the eight MSBs of the t4 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t4 edge. 0 = no PWM modulation of the t4 edge. 1 = negative sign. Increase of PWM modulation moves t4 right. 0 = positive sign. Increase of PWM modulation moves t4 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t4 sign Reserved
R/W R/W R/W
Table 68. Register 0x49--OUTC Rising Edge Timing (OUTC Pin)
Bits [7:0] Name t5 R/W R/W Description This register contains the eight MSBs of the 12-bit t5 time. This value is always used with the top four bits of Register 0x4A, which contains the four LSBs of the t5 time. Each LSB corresponds to 5 ns resolution.
Table 69. Register 0x4A--OUTC Rising Edge Setting (OUTC Pin)
Bits [7:4] Name t5 R/W R/W Description These bits contain the four LSBs of the 12-bit t5 time. This value is always used with the eight bits of Register 0x49, which contains the eight MSBs of the t5 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t5 edge. 0 = no PWM modulation of the t5 edge. 1 = negative sign. Increase of PWM modulation moves t5 right. 0 = positive sign. Increase of PWM modulation moves t5 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t5 sign Reserved
R/W R/W R/W
Table 70. Register 0x4B--OUTC Falling Edge Timing (OUTC Pin)
Bits [7:0] Name t6 R/W R/W Description This register contains the eight MSBs of the 12-bit t6 time. This value is always used with the top four bits of Register 0x4C, which contains the four LSBs of the t6 time. Each LSB corresponds to 5 ns resolution.
Table 71. Register 0x4C--OUTC Falling Edge Setting (OUTC Pin)
Bits [7:4] Name t6 R/W R/W Description These bits contain the four LSBs of the 12-bit t6 time. This value is always used with the eight bits of Register 0x4B, which contains the eight MSBs of the t6 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t6 edge. 0 = no PWM modulation of the t6 edge. 1 = negative sign. Increase of PWM modulation moves t6 right. 0 = positive sign. Increase of PWM modulation moves t6 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t6 sign Reserved
R/W R/W R/W
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ADP1043A
Table 72. Register 0x4D--OUTD Rising Edge Timing (OUTD Pin)
Bits [7:0] Name t7 R/W R/W Description This register contains the eight MSBs of the 12-bit t7 time. This value is always used with the top four bits of Register 0x4E, which contains the four LSBs of the t7 time. Each LSB corresponds to 5 ns resolution.
Table 73. Register 0x4E--OUTD Rising Edge Setting (OUTD Pin)
Bits [7:4] Name t7 R/W R/W Description These bits contain the four LSBs of the 12-bit t7 time. This value is always used with the eight bits of Register 0x4D, which contains the eight MSBs of the t7 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t7 edge. 0 = no PWM modulation of the t7 edge. 1 = negative sign. Increase of PWM modulation moves t7 right. 0 = positive sign. Increase of PWM modulation moves t7 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t7 sign Reserved
R/W R/W R/W
Table 74. Register 0x4F--OUTD Falling Edge Timing (OUTD Pin)
Bits [7:0] Name t8 R/W R/W Description This register contains the eight MSBs of the 12-bit t8 time. This value is always used with the top four bits of Register 0x50, which contains the four LSBs of the t8 time. Each LSB corresponds to 5 ns resolution.
Table 75. Register 0x50--OUTD Falling Edge Setting (OUTD Pin)
Bits [7:4] Name t8 R/W R/W Description These bits contain the four LSBs of the 12-bit t8 time. This value is always used with the eight bits of Register 0x4F, which contains the eight MSBs of the t8 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t8 edge. 0 = no PWM modulation of the t8 edge. 1 = negative sign. Increase of PWM modulation moves t8 right. 0 = positive sign. Increase of PWM modulation moves t8 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t8 sign Reserved
R/W R/W R/W
Table 76. Register 0x51--SR1 Rising Edge Timing (SR1 Pin)
Bits [7:0] Name t9 R/W R/W Description This register contains the eight MSBs of the 12-bit t9 time. This value is always used with the top four bits of Register 0x52, which contains the four LSBs of the t9 time. Each LSB corresponds to 5 ns resolution.
Table 77. Register 0x52--SR1 Rising Edge Setting (SR1 Pin)
Bits [7:4] Name t9 R/W R/W Description These bits contain the four LSBs of the 12-bit t9 time. This value is always used with the eight bits of Register 0x51, which contains the eight MSBs of the t9 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t9 edge. 0 = no PWM modulation of the t9 edge. 1 = negative sign. Increase of PWM modulation moves t9 right. 0 = positive sign. Increase of PWM modulation moves t9 left. 1 = volt-second balance circuit modulates SR1 and SR2, along with OUTB and OUTD. When this bit is set, the volt-second balance modulation is applied to the rising edge of SR1 and SR2. Reserved. This bit should be set to 0 for normal operation.
3 2 1 0
Modulate enable t9 sign VS balance with SR1 and SR2 Reserved
R/W R/W R/W R/W
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ADP1043A
Table 78. Register 0x53--SR1 Falling Edge Timing (SR1 Pin)
Bits [7:0] Name t10 R/W R/W Description This register contains the eight MSBs of the 12-bit t10 time. This value is always used with the top four bits of Register 0x54, which contains the four LSBs of the t10 time. Each LSB corresponds to 5 ns resolution.
Table 79. Register 0x54--SR1 Falling Edge Setting (SR1 Pin)
Bits [7:4] Name t10 R/W R/W Description These bits contain the four LSBs of the 12-bit t10 time. This value is always used with the eight bits of Register 0x53, which contains the eight MSBs of the t10 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t10 edge. 0 = no PWM modulation of the t10 edge. 1 = negative sign. Increase of PWM modulation moves t10 right. 0 = positive sign. Increase of PWM modulation moves t10 left. 1 = SR signals perform a soft start every time that they are enabled. 0 = SR signals perform a soft start only the first time that they are enabled. Setting this bit enables the soft start function for the SR signals.
3 2 1 0
Modulate enable t10 sign SR soft start setting SR soft start enable
R/W R/W R/W R/W
Table 80. Register 0x55--SR2 Rising Edge Timing (SR2 Pin)
Bits [7:0] Name t11 R/W R/W Description This register contains the eight MSBs of the 12-bit t11 time. This value is always used with the top four bits of Register 0x56, which contains the four LSBs of the t11 time. Each LSB corresponds to 5 ns resolution.
Table 81. Register 0x56--SR2 Rising Edge Setting (SR2 Pin)
Bits [7:4] Name t11 R/W R/W Description These bits contain the four LSBs of the 12-bit t11 time. This value is always used with the eight bits of Register 0x55, which contains the eight MSBs of the t11 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t11 edge. 0 = no PWM modulation of the t11 edge. 1 = negative sign. Increase of PWM modulation moves t11 right. 0 = positive sign. Increase of PWM modulation moves t11 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t11 sign Reserved
R/W R/W R/W
Table 82. Register 0x57--SR2 Falling Edge Timing (SR2 Pin)
Bits [7:0] Name t12 R/W R/W Description This register contains the eight MSBs of the 12-bit t12 time. This value is always used with the top four bits of Register 0x58, which contains the four LSBs of the t12 time. Each LSB corresponds to 5 ns resolution.
Table 83. Register 0x58--SR2 Falling Edge Setting (SR2 Pin)
Bits [7:4] Name t12 R/W R/W Description These bits contain the four LSBs of the 12-bit t12 time. This value is always used with the eight bits of Register 0x57, which contains the eight MSBs of the t12 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t12 edge. 0 = no PWM modulation of the t12 edge. 1 = negative sign. Increase of PWM modulation moves t12 right. 0 = positive sign. Increase of PWM modulation moves t12 left. Reserved. These bits should be set to 00 for normal operation.
3 2 [1:0]
Modulate enable t12 sign Reserved
R/W R/W R/W
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ADP1043A
Table 84. Register 0x59--OUTAUX Rising Edge Timing (OUTAUX Pin)
Bits [7:0] Name t13 R/W R/W Description This register contains the eight MSBs of the 12-bit t13 time. This value is always used with the top four bits of Register 0x5A, which contains the four LSBs of the t13 time. Each LSB corresponds to 5 ns resolution.
Table 85. Register 0x5A--OUTAUX Rising Edge Setting (OUTAUX Pin)
Bits [7:4] Name t13 R/W R/W Description These bits contain the four LSBs of the 12-bit t13 time. This value is always used with the eight bits of Register 0x59, which contains the eight MSBs of the t13 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t13 edge. 0 = no PWM modulation of the t13 edge. 1 = negative sign. Increase of PWM modulation moves t13 right. 0 = positive sign. Increase of PWM modulation moves t13 left. Reserved. Set these bits to 00 for normal operation.
3 2 [1:0]
Modulate enable t13 sign Reserved
R/W R/W R/W
Table 86. Register 0x5B--OUTAUX Falling Edge Timing (OUTAUX Pin)
Bits [7:0] Name t14 R/W R/W Description This register contains the eight MSBs of the 12-bit t14 time. This value is always used with the top four bits of Register 0x5C, which contains the four LSBs of the t14 time. Each LSB corresponds to 5 ns resolution.
Table 87. Register 0x5C--OUTAUX Falling Edge Setting (OUTAUX Pin)
Bits [7:4] Name t14 R/W R/W Description These bits contain the four LSBs of the 12-bit t14 time. This value is always used with the eight bits of Register 0x5B, which contains the eight MSBs of the t14 time. Each LSB corresponds to 5 ns resolution. 1 = PWM modulation acts on the t14 edge. 0 = no PWM modulation of the t14 edge. 1 = negative sign. Increase of PWM modulation moves t14 right. 0 = positive sign. Increase of PWM modulation moves t14 left. 1 = control loop PWM modulation is regulated by OUTAUX. When this bit is set, the CS1 blanking signal is synchronized with OUTAUX. 0 = control loop PWM modulation is regulated by OUTA, OUTB, OUTC, OUTD, SR1, and SR2 (normal mode). Reserved. Set this bit to 0 for normal operation.
3 2 1
Modulate enable t14 sign Regulate with OUTAUX
R/W R/W R/W
0
Reserved
R/W
Table 88. Register 0x5D--OUTx and SRx Pin Disable Setting
Bits 7 6 5 4 3 2 1 0 Name OUTAUX disable SR2 disable SR1 disable OUTD disable OUTC disable OUTB disable OUTA disable GO R/W R/W R/W R/W R/W R/W R/W R/W W Description Setting this bit disables the OUTAUX output. Setting this bit disables the SR2 output. Setting this bit disables the SR1 output. Setting this bit disables the OUTD output. Setting this bit disables the OUTC output. Setting this bit disables the OUTB output. Setting this bit disables the OUTA output. This bit latches in all registers from Address 0x3F to Address 0x5D. This bit prevents the PWM timing from being temporarily incorrect, if changing PWM timing while the power supply is on. This bit also latches in any changes made to Register 0x31 (VS3 voltage setting).
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ADP1043A
Table 89. Register 0x5E--Password Lock
Bits [7:0] Name Password R/W W Description This register contains the 8-bit EEPROM lock password. This password is used to protect the register contents from being changed. The EEPROM is always locked. When the EEPROM downloads its contents to the registers, the password is also downloaded. If the user writes the same password to this register twice, the EEPROM is unlocked and can be updated. To lock the EEPROM again, the user must write any value other than the password value into this register.
DIGITAL FILTER PROGRAMMING REGISTERS
LF GAIN RANGE 20dB
HF GAIN RANGE
5kHz
POLE ZERO
ZERO RANGE
POLE LOCATION RANGE
Figure 37. Digital Filter Programmability
Table 90. Register 0x5F--Soft Start Digital Filter LF Gain Setting
Bits [7:2] [1:0] Name Reserved Soft start filter gain R/W R/W R/W Description Reserved. These bits set the gain of the low-pass digital filter that is used during soft start. Bit 1 Bit 0 Filter Gain 0 0 1 0 1 2 1 0 4 1 1 8
Table 91. Register 0x60--Normal Mode Digital Filter LF Gain Setting
Bits [7:0] Name LF gain setting R/W R/W Description This register determines the low frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37.
Table 92. Register 0x61--Normal Mode Digital Filter Zero Setting
Bits [7:0] Name Zero setting R/W R/W Description This register determines the position of the final 0. See Figure 37.
Table 93. Register 0x62--Normal Mode Digital Filter Pole Setting
Bits [7:0] Name Pole location R/W R/W Description This register determines the position of the final pole. See Figure 37.
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08501-036
100Hz
500Hz
1kHz
20dB
10kHz
20dB
ADP1043A
Table 94. Register 0x63--Normal Mode Digital Filter HF Gain Setting
Bits [7:0] Name HF gain setting R/W R/W Description This register determines the high frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37.
Table 95. Register 0x64--Light Load Mode Digital Filter LF Gain Setting
Bits [7:0] Name LF gain setting R/W R/W Description This register determines the low frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37.
Table 96. Register 0x65--Light Load Mode Digital Filter Zero Setting
Bits [7:0] Name Zero setting R/W R/W Description This register determines the position of the final 0. See Figure 37.
Table 97. Register 0x66--Light Load Mode Digital Filter Pole Setting
Bits [7:0] Name Pole location R/W R/W Description This register determines the position of the final pole. See Figure 37.
Table 98. Register 0x67--Light Load Mode Digital Filter HF Gain Setting
Bits [7:0] Name HF gain setting R/W R/W Description This register determines the high frequency gain of the loop response. Programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 37.
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ADP1043A
ADAPTIVE DEAD TIME REGISTERS
Table 99. Register 0x68--Dead Time Threshold
Bits [7:3] [2:0] Name Reserved Adaptive dead time threshold R/W R/W R/W Description Reserved. This value determines the adaptive dead time threshold. Below this threshold, the offsets from Register 0x69 to Register 0x6F are introduced. Threshold for Each Nominal CS2 Setting (mV) 37.5 mV Setting 75 mV Setting 150 mV Setting Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 1 3.9 7.8 15.6 0 1 0 7.8 15.6 31.25 0 1 1 11.7 23.5 47 1 0 0 15.5 31 62.5 1 0 1 19.5 39 78 1 1 0 23.5 47 94 1 1 1 27 54 109
Table 100. Register 0x69--Dead Time 1
Bits 7 [6:4] Name t1 polarity t1 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t1 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t2 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t2 polarity t2 offset
R/W R/W
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ADP1043A
Table 101. Register 0x6A--Dead Time 2
Bits 7 [6:4] Name t3 polarity t3 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t3 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t4 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t4 polarity t4 offset
R/W R/W
Table 102. Register 0x6B--Dead Time 3
Bits 7 [6:4] Name t5 polarity t5 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t5 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t6 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t6 polarity t6 offset
R/W R/W
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ADP1043A
Table 103. Register 0x6C--Dead Time 4
Bits 7 [6:4] Name t7 polarity t7 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t7 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t8 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t8 polarity t8 offset
R/W R/W
Table 104. Register 0x6D--Dead Time 5
Bits 7 [6:4] Name t9 polarity t9 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t9 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t10 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t10 polarity t10 offset
R/W R/W
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ADP1043A
Table 105. Register 0x6E--Dead Time 6
Bits 7 [6:4] Name t11 polarity t11 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t11 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t12 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t12 polarity t12 offset
R/W R/W
Table 106. Register 0x6F--Dead Time 7
Bits 7 [6:4] Name t13 polarity t13 offset R/W R/W R/W Description 0 = positive polarity; 1 = negative polarity. This value determines the t13 offset from the nominal timing. Bit 6 Bit 5 Bit 4 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35 0 = positive polarity; 1 = negative polarity. This value determines the t14 offset from the nominal timing. Bit 2 Bit 1 Bit 0 Offset (ns) 0 0 0 0 0 0 1 5 0 1 0 10 0 1 1 15 1 0 0 20 1 0 1 25 1 1 0 30 1 1 1 35
3 [2:0]
t14 polarity t14 offset
R/W R/W
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ADP1043A
EEPROM REGISTERS
Table 107. Register 0x7B--EEPROM Restore Factory Default Register Settings
Bits [7:0] Name EEPROM restore factory default settings R/W R/W Description The user can write one of the following command codes to this register to perform a specific EEPROM operation: 0x00: Upload registers to Page 0 of the main block (user settings). 0x01: Download factory settings (factory block) to the registers. 0x02: Page erase operation. For more information, see the EEPROM section.
Table 108. Register 0x7C--EEPROM X Address
Bits 7 [6:0] Name Reserved EEPROM X address R/W R/W R/W Description Reserved. This register is used to point to the page and row of the byte to be accessed in EEPROM main memory. Bits[6:3] select one of 16 pages in the main block; Bits[2:0] select one of eight rows on the selected page. The byte to be accessed is specified using Register 0x7D. For more information, see the EEPROM section.
Table 109. Register 0x7D--EEPROM Y Address
Bits [7:6] [5:0] Name Reserved EEPROM Y address R/W R/W R/W Description Reserved. This register is used to point to the byte to be accessed in EEPROM main memory. The page and row of the byte are specified using Register 0x7C. For more information, see the EEPROM section.
Table 110. Register 0x7E--EEPROM Register
Bits [7:0] Name EEPROM register R/W R/W Description Read or write to this register to read or program a byte in EEPROM main memory. For more information, see the EEPROM section.
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ADP1043A RESONANT MODE OPERATION
The ADP1043A supports control of a resonant converter. Resonant converters are an alternative to traditional fixed frequency converters. They offer high switching frequency, small size, and high efficiency. Figure 38 illustrates a widely used series resonant converter.
QA QC CR IR QD QB LR IO SR1 CO RL SR2
SYNCHRONOUS RECTIFICATION IN RESONANT MODE
Control of the synchronous rectifiers in a resonant controller is a complicated issue. The ADP1043A ACSNS comparator can be used to control the SR signals. In resonant mode operation, the SR1 output is driven by the rising edge of the ACSNS comparator, and the SR2 output is driven by the falling edge of the comparator, as shown in Figure 40.
VDS (SR2)
08501-037
Figure 38. Series Resonant Converter
ACSNS
RESONANT MODE ENABLE
To enable the ADP1043A to control a resonant switching converter, Register 0x40 must be set to a value of 0x3F. In resonant mode, the PWM outputs have a fixed duty cycle with variable frequency.
SYNC RECT 1 (SR1)
t9
t10
SYNC RECT 2 (SR2)
t11 tD tE tF
t12
08501-040
PWM TIMING IN RESONANT MODE
With variable frequency control, OUTA and OUTB can only be high during the first half of the switching cycle (tA to tB), whereas OUTC and OUTD can only be high during the second half of the switching cycle (tB to tC), as shown in Figure 39.
PWM1 (OUTA)
Figure 40. SR1 and SR2 PWM Timing Diagram in Resonant Mode
t1
t2
Following is an example of how the ADP1043A can be used in a series resonant topology and also achieve control of the synchronous rectifiers. The VDS voltage of SR2 can be used to control the SR signals. The ACSNS pin is connected to the divided-down SR2 VDS voltage. This provides the timing information for both synchronous rectifiers (see Figure 41).
SR2 CR IR LR IO SR1 CO RL R2 R1 ACSNS
PWM2 (OUTB)
t3
t4
PWM3 (OUTC)
t5
t6
Figure 41. Resonant Synchronous Rectifier Control Circuit
PWM4 (OUTD)
t7
t8
tA
tB
tC
Figure 39. OUTA, OUTB, OUTC, and OUTD PWM Timing Diagram in Resonant Mode
08501-038
tPERIOD
tPERIOD
After the timing information is obtained, SR1 is driven by the rising edge of the ACSNS comparator, and SR2 is driven by the falling edge of the comparator, as shown in Figure 40. In this way, it is possible to achieve synchronous rectification. Turn-on and turn-off delays can be programmed for the SR1 and SR2 signals individually. This example is not the only way to control the SR signals. If the user has another method to control the SR signals, this method can be used to connect to the ACSNS input instead of the VDS voltage of SR2.
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08501-039
ADP1043A
ADJUSTING THE TIMING OF THE PWM OUTPUTS
To accurately adjust the timing of the PWM outputs, the following registers can be used to set the dead time and delays of the PWM outputs: Register 0x41, Register 0x43, Register 0x45, Register 0x47, Register 0x49, Register 0x4B, Register 0x4D, Register 0x4F, Register 0x51, Register 0x53, Register 0x55, and Register 0x57. The resolution for adjusting the dead time is 5 ns. Refer to the Resonant Mode Register Descriptions section for more detailed information. The software GUI for the ADP1043A can be used to set the frequency limit registers, as well as all other settings related to the resonant mode of operation.
SOFT START IN RESONANT MODE
During soft start, the reference voltage of the ADP1043A ramps up. With the feedback loop closed, the switching frequency is reduced from the highest limit to a regulation value. The soft start timing settings and the filter settings are the same as those for the fixed frequency PWM mode (see the Soft Start section).
LIGHT LOAD OPERATION (BURST MODE)
To control the converter at very light load, the ADP1043A can operate in burst mode. Burst mode can be enabled or disabled using Bits[7:6] of Register 0x4A. When the desired switching frequency is higher than the burst mode threshold, the part enters burst mode. The threshold is determined by the maximum frequency and the burst mode offset setting. The threshold value used to enter burst mode is determined as follows:
Threshold value for burst mode = ((Register 0x46 x 16) + Register 0x48[7:4]) + (Register 0x4A[5:0] x 2)
FREQUENCY LIMIT SETTING
The minimum frequency is set by Register 0x42 and by the first four bits of Register 0x44. For example, Register 0x42 is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal). The maximum switching cycle is (160 x 16 + 15) x 5 ns = 12.875 s The lowest switching frequency limit is 1/12.875 s = 77.7 kHz The maximum frequency is set by Register 0x46 and by Bits[7:4] of Register 0x48. For example, Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal). The minimum switching cycle is (16 x 16 + 9) x 5 ns = 1.325 s The highest switching frequency limit is 1/1.325 s = 755 kHz
The threshold value used to exit burst mode is determined by the entrance value plus 0x10. For example, Register 0x46 is set to 0x10 (16 decimal), Bits[7:4] of Register 0x48 are set to 0, and Bits[5:0] of Register 0x4A are set to 0x8 (8 decimal). The minimum switching cycle is (16 x 16 + 0) x 5 ns = 1.28 s The highest switching frequency limit is 1/1.28 s = 781 kHz The threshold to enter burst mode is [(16 x 16 + 0) + (8 x 2)] x 5 ns = 1.36 s When the desired switching frequency is higher than 1/1.36 s = 735 kHz, the PWM outputs are shut down and the part enters burst mode. The threshold to exit burst mode is [(16 x 16 + 0) + (8 x 2) + 16] x 5 ns = 1.44 s Therefore, when the desired switching frequency becomes lower than 1/1.44 s = 694 kHz, the PWM signals are reenabled, and the part exits burst mode.
FEEDBACK CONTROL IN RESONANT MODE
In contrast to a traditional fixed frequency PWM converter, the output voltage of a resonant converter is regulated by changing the switching frequency. When the ADP1043A is operated in resonant mode, the switching frequency decreases when the sensed voltage is lower than the reference voltage. This makes the ADP1043A capable of controlling a resonant converter in zero-voltage switching (ZVS) mode. Although the switching frequency is variable, the feedback voltage sampling frequency is fixed at 400 kHz. The parameters of the feedback filter are based on this frequency. The method for calculating the filter parameters (gains, zeros, and poles) is the same as that for the fixed frequency PWM mode (see the Digital Filter section).
OUTAUX IN RESONANT MODE
In resonant mode, the OUTAUX pin cannot be used as a control signal. However, OUTAUX can be used as a fixed frequency PWM signal with a fixed duty cycle.
PROTECTIONS IN RESONANT MODE
All of the flags and protections that are available in resonant mode behave in the same manner as in fixed frequency PWM mode.
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ADP1043A
RESONANT MODE REGISTER DESCRIPTIONS
Table 111. Register 0x40--PWM Switching Frequency Setting in Resonant Mode
Bits [7:6] [5:0] Name Reserved Switching frequency R/W R/W R/W Description Reserved. This register sets the switching frequency of the PWM pins and enables resonant mode. To enable resonant mode, set these bits to 0x3F (11 1111).
Table 112. Register 0x41--OUTA Rising Edge Dead Time in Resonant Mode
Bits [7:0] Name t1 (rising edge dead time of OUTA) R/W R/W Description This register sets t1, which is the delay of the rising edge of OUTA from the start of the switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t1 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 113. Register 0x42--Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode)
Bits [7:0] Name Lowest frequency R/W R/W Description This register contains the eight MSBs of the 12-bit value of the lowest switching frequency (maximum switching cycle) limit. This value is always used with the top four bits of Register 0x44, which contain the four LSBs of the lowest switching frequency limit. Each LSB of the 12-bit value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x42 is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the maximum switching cycle is (160 x 16 + 15) x 5 ns = 12.875 s, and the lowest switching frequency limit is 1/12.875 s = 77.7 kHz.
Table 114. Register 0x43--OUTA Falling Edge Dead Time in Resonant Mode
Bits [7:0] Name t2 (falling edge dead time of OUTA) R/W R/W Description This register sets t2, which is the difference between the falling edge of OUTA and the midpoint of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the falling edge of OUTA is trailing tB. When the value is from 0x80 to 0xFF, the falling edge of OUTA is leading tB. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t2 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing ... ... ... ... ... ... ... ... ... 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 5 ns leading
Table 115. Register 0x44--Lowest Switching Frequency Limit Setting (Maximum Switching Cycle in Resonant Mode)
Bits [7:4] Name Lowest frequency R/W R/W Description This register contains the four LSBs of the 12-bit value of the lowest switching frequency (maximum switching cycle) limit. This value is always used with the eight bits of Register 0x42, which contain the eight MSBs of the lowest switching frequency limit. Each LSB of the 12-bit value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x42 is set to 0xA0 (160 decimal) and Bits[7:4] of Register 0x44 are set to 0xF (15 decimal), the maximum switching cycle is (160 x 16 + 15) x 5 ns = 12.875 s, and the lowest switching frequency limit is 1/12.875 s = 77.7 kHz. Reserved.
[3:0]
Reserved
R/W
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ADP1043A
Table 116. Register 0x45--OUTB Rising Edge Dead Time in Resonant Mode
Bits [7:0] Name t3 (rising edge dead time of OUTB) R/W R/W Description This register sets t3, which is the delay time of the rising edge of OUTB from the start of the switching cycle, tA. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t3 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 117. Register 0x46--Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)
Bits [7:0] Name Highest frequency R/W R/W Description This register contains the eight MSBs of the 12-bit value of the highest switching frequency (minimum switching cycle) limit. This value is always used with the top four bits of Register 0x48, which contain the four LSBs of the highest switching frequency limit. Each LSB of the 12-bit value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum switching cycle is (16 x 16 + 9) x 5 ns = 1.325 s, and the highest switching frequency limit is 1/1.325 s = 755 kHz.
Table 118. Register 0x47--OUTB Falling Edge Dead Time in Resonant Mode
Bits [7:0] Name t4 (falling edge dead time of OUTB) R/W R/W Description This register sets t4, which is the difference between the falling edge of OUTB and the midpoint of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the falling edge of OUTB is trailing tB. When the value is from 0x80 to 0xFF, the falling edge of OUTB is leading tB. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t4 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing ... ... ... ... ... ... ... ... ... 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 5 ns leading
Table 119. Register 0x48--Highest Switching Frequency Limit Setting (Minimum Switching Cycle in Resonant Mode)
Bits [7:4] Name Highest frequency R/W R/W Description This register contains the four LSBs of the 12-bit value of the highest switching frequency (minimum switching cycle) limit. This value is always used with the eight bits of Register 0x46, which contain the eight MSBs of the highest switching frequency limit. Each LSB of the 12-bit value corresponds to 5 ns of resolution for the switching cycle. For example, if Register 0x46 is set to 0x10 (16 decimal) and Bits[7:4] of Register 0x48 are set to 0x9 (9 decimal), the minimum switching cycle is (16 x 16 + 9) x 5 ns = 1.325 s, and the highest switching frequency limit is 1/1.325 s = 755 kHz. Reserved.
[3:0]
Reserved
R/W
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ADP1043A
Table 120. Register 0x49--OUTC Rising Edge Dead Time in Resonant Mode
Bits [7:0] Name t5 (rising edge dead time of OUTC) R/W R/W Description This register sets t5, which is the difference between the rising edge of OUTC and the midpoint of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the rising edge of OUTC is trailing tB. When the value is from 0x80 to 0xFF, the rising edge of OUTC is leading tB. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t5 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing ... ... ... ... ... ... ... ... ... 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 5 ns leading
Table 121. Register 0x4A--Burst Mode Operation in Resonant Mode
Bits [7:6] Name Burst mode enable R/W R/W Description These bits are used to enable or disable burst mode operation. Bit 7 Bit 6 Burst Mode 0 0 Disabled 0 1 Enabled for normal operation, but disabled during soft start 1 0 Disabled 1 1 Enabled for normal operation and during soft start These bits, along with the highest switching frequency limit, determine the threshold value for enabling burst mode operation. For information about how to set this value, see the Light Load Operation (Burst Mode) section.
[5:0]
Burst mode offset
R/W
Table 122. Register 0x4B--OUTC Falling Edge Dead Time in Resonant Mode
Bits [7:0] Name t6 (falling edge dead time of OUTC) R/W R/W Description This register sets t6, which is the leading time of the falling edge of OUTC from the end of the switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t6 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 123. Register 0x4D--OUTD Rising Edge Dead Time in Resonant Mode
Bits [7:0] Name t7 (rising edge dead time of OUTD) R/W R/W Description This register sets t7, which is the difference between the rising edge of OUTD and the midpoint of the switching cycle, tB. Each LSB corresponds to 5 ns of resolution. When the register value is from 0x00 to 0x7F, the rising edge of OUTD is trailing tB. When the value is from 0x80 to 0xFF, the rising edge of OUTD is leading tB. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t7 0 0 0 0 0 0 0 0 0 ns 0 0 0 0 0 0 0 1 5 ns trailing ... ... ... ... ... ... ... ... ... 0 1 1 1 1 1 1 1 635 ns trailing 1 0 0 0 0 0 0 0 640 ns leading ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 5 ns leading
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ADP1043A
Table 124. Register 0x4F--OUTD Falling Edge Dead Time in Resonant Mode
Bits [7:0] Name t8 (falling edge dead time of OUTD) R/W R/W Description This register sets t8, which is the leading time of the falling edge of OUTD from the end of the switching cycle, tC. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t8 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 125. Register 0x51--SR1 Rising Edge Dead Time in Resonant Mode
Bits [7:0] Name t9 (rising edge dead time of SR1) R/W R/W Description This register sets t9, which is the delay time of the rising edge of SR1 from the ACSNS rising edge, tD. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t9 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 126. Register 0x53--SR1 Falling Edge Dead Time in Resonant Mode
Bits [7:0] Name t10 (falling edge dead time of SR1) R/W R/W Description This register sets t10, which is the leading time of the falling edge of SR1 from the ACSNS falling edge, tE. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t10 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 127. Register 0x55--SR2 Rising Edge Dead Time in Resonant Mode
Bits [7:0] Name t11 (rising edge dead time of SR2) R/W R/W Description This register sets t11, which is the delay time of the rising edge of SR2 from the ACSNS falling edge, tE. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t11 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
Table 128. Register 0x57--SR2 Falling Edge Dead Time in Resonant Mode
Bits [7:0] Name t12 (falling edge dead time of SR2) R/W R/W Description This register sets t12, which is the leading time of the falling edge of SR2 from the ACSNS rising edge, tF. Each LSB corresponds to 5 ns of resolution. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 t12 (ns) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 ... ... ... ... ... ... ... ... ... 1 1 1 1 1 1 1 1 1275
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ADP1043A OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
17 16 8
3.25 3.10 SQ 2.95
0.50 0.40 0.30
9
0.25 MIN 3.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP1043AACPZ-RL 1
1
Temperature Range -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
011708-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Package Option CP-32-2
Z = RoHS Compliant Part.
Rev. 0 | Page 71 of 72
ADP1043A NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08501-0-10/09(0)
Rev. 0 | Page 72 of 72

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